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View all- Ichikawa SSato MGoto E(2007)Evaluation of range‐checking addressing modes and the architecture of FLATS2Systems and Computers in Japan10.1002/scj.469023100123:10(1-13)Online publication date: 21-Mar-2007
Run-time checking in Lisp by integrating memory addressing and range checking
Authors: 
M. Sato, S. Ichikawa, E. GotoAuthors Info & Claims
M. Sato, S. Ichikawa, E. GotoAuthors Info & ClaimsPages 290 - 297
Abstract
This paper describes the BL addressing mode and the address tag in FLATS2 machine, which is a general-purpose MIMD computer now under construction. The BL addressing mode integrates memory accessing and range checking by hardware. Address tag is a bit in word, which indicates the capability for memory access. Combining them together, efficient memory protection is provided at run-time. It reduces the cost of run-time type checking in Lisp by checking the address tag and the address of a pointer against the range of the region associated to a type, in parallel with the memory access. The arithmetic instructions check the address tags of operands to support the generic arithmetic in Lisp. We can also make use of this scheme to check the number of arguments and multiple return values and to check array-bounds to support faster execution of Common Lisp program. These facilities are not specific to Lisp, so that they can be used more generally than other tagged architectures.
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Published: 01 April 1989
Published in SIGARCH Volume 17, Issue 3
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View all- Ichikawa SSato MGoto E(2007)Evaluation of range‐checking addressing modes and the architecture of FLATS2Systems and Computers in Japan10.1002/scj.469023100123:10(1-13)Online publication date: 21-Mar-2007
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