A 553 k-transistor lisp processor chip
PW Bosshart, CR Hewes, MD Ales…�- IEEE journal of solid�…, 1987 - ieeexplore.ieee.org
PW Bosshart, CR Hewes, MD Ales, MC Chang, KK Chau, K Fasham, CC Hoac, TW Houston…
IEEE journal of solid-state circuits, 1987•ieeexplore.ieee.orgThe authors describe a LISP microprocessor which includes over 550 K transistors, has 114
K of on-chip RAM, and runs instructions in a single 30-ns clock cycle. The chip is
implemented in 1.25-/spl mu/m double-level-metal (DLM) CMOS, has 224 pins, and is
packaged in a custom pin-grid array. The microinstruction and macroinstruction sets of this
chip are compatible with an existing LISP processor. An extensive discussion of test features
designed into the processor chip is given.
K of on-chip RAM, and runs instructions in a single 30-ns clock cycle. The chip is
implemented in 1.25-/spl mu/m double-level-metal (DLM) CMOS, has 224 pins, and is
packaged in a custom pin-grid array. The microinstruction and macroinstruction sets of this
chip are compatible with an existing LISP processor. An extensive discussion of test features
designed into the processor chip is given.
The authors describe a LISP microprocessor which includes over 550 K transistors, has 114 K of on-chip RAM, and runs instructions in a single 30-ns clock cycle. The chip is implemented in 1.25-/spl mu/m double-level-metal (DLM) CMOS, has 224 pins, and is packaged in a custom pin-grid array. The microinstruction and macroinstruction sets of this chip are compatible with an existing LISP processor. An extensive discussion of test features designed into the processor chip is given.
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