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A case study for the application of deterministic and stochastic Petri nets in the SoC communication domain. (English) Zbl 1103.68650

Summary: This paper presents an approach utilizing deterministic and stochastic Petri nets to analyze on-chip communication. In order to demonstrate the suitability of this approach, the on-chip communication structure of two examples featuring typical System-on-Chip (SoC) communication conflicts like competition for common communication resources have been studied. A state-of-the-art heterogeneous digital signal processor and a design example with an on-chip bus have been examined. The results show that sufficient modeling accuracy can be achieved with low modeling effort in terms of computation and implementation time.

MSC:

68Q85 Models and methods for concurrent and distributed computing (process algebras, bisimulation, transition nets, etc.)
Full Text: DOI

References:

[1] M. Ajmone Marsan, G. Chiola, ”On Petri Nets with Deterministic and Exponentially Distributed Firing Times,” in G. Rozenberg (Ed.) Advances in Petri Nets 1986, Lecture Notes in Computer Science Vol. 266, Springer 1987, pp. 146–161.
[2] ARM AMBA; http://www.arm.com/products/solutions/AMBAHomePage.html
[3] H. Blume, H. Feldkämper, T. G. Noll, ”Model-based Exploration of the Design Space for Heterogeneous Systems-on-Chip,” Journal of VLSI-Signal Processing Vol. 40, (1), 2005, pp. 19–34. · doi:10.1007/s11265-005-4936-4
[4] DSPNexpress; http://www.dspnexpress.de · Zbl 0818.68116
[5] M. Franklin, T. Wolf, ”A network processor performance and design model with benchmark parameterization,” in Network Processor Design: Issues and Practices, Vol. 1, Morgan Kaufmann, 2003, ch. 6, pp. 117–140.
[6] IBM CoreConnect; http://www-03.ibm.com/chips/products/coreconnect
[7] L. Kleinrock, ”Queueing Systems– Vol. 1: Theory,” JOHN WILEY AND SONS, 1975. · Zbl 0334.60045
[8] T. Kogel, M. Doerper, A. Wieferink, et. al. ”A Modular Simulation Framework for Architectural Exploration of On-Chip Interconnection Networks,” CODES+ISSS, Oct. 2003.
[9] K. Lahiri, A. Raghunathan, S. Dey, ”Evaluation of the traffic performance characteristics of system-on-chip architectures,” Proc. VLSI Design, Jan. 2001, pp. 29–35.
[10] K. Lahiri, A. Raghunathan, S. Dey, ”System-Level Performance Analysis for Designing On-Chip Communication Architectures”, IEEE Trans. on CAD of Integrated Circuits and Systems, Jun. 01
[11] A. Ledeczi, J. Davis, S. Neema, A. Agrawal, ”Modeling Methodology for Multi-Granular Simulation of Embedded Systems,” 2002, http://milan.usc.edu/documents.html
[12] C. Lindemann, ”Performance Modeling with Deterministic and Stochastic Petri Nets,” JOHN WILEY AND SONS, Berlin, 1998. · Zbl 0897.68012
[13] J. Madsen, S. Mahadevan, K. Virk, ”Network-Centric System-Level Model for Multiprocessor SoC Simulation,” in Interconnect Centric Design for Advanced SoC and NoC, J. Nurmi, et. al. (Eds.), Kluwer Academic Publishers, 2004.
[14] M. H. Mickle, ”Transient and steady-state performance modeling of parallel processors,” Applied Mathematical Modelling Vol. 22, No. 7, Jul. 1998, pp. 533–543.
[15] C. A. Petri, ”Communication with Automatas,” PhD Dissertation University of Bonn, 1962 (in German).
[16] Petri net tools data base; http://www.daimi.au.dk/PetriNets
[17] A. Pimentel, L. Hertzberger, P. Lieverse, P. van der Wolf, E. Deprettere, ”Exploring Embedded System Architectures with Artemis,” IEEE Computer, Vol. 34, Nr. 11, Nov. 2001, pp. 57–63.
[18] A. Pimentel, F. Terpstra, S. Polstra, J. Coffland, ”Modelling of Intra-task Parallelism in Task-level Parallel Embedded Systems,” in Domain-Specific Processors: Systems, Architectures, Modeling, and Simulation Marcel Dekker, Inc., 2003.
[19] Texas Instruments; http://www.ti.com · Zbl 0819.68013
[20] L. Thiele, E. Wandeler, S. Chakraborty, ”Performance Analysis of Multiprocessor DSPs,” IEEE Signal Processing Magazine, 22 (3), May 2005, pp. 38–46. · doi:10.1109/MSP.2005.1425896
[21] TimeNET; http://pdv.cs.tu-berlin.de/\(\sim\)timenet/
[22] VCC, Cadence virtual component codesign; http://www.cadence.com/products/vcc.html
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