Jaberipur, Ghassem; Parhami, Behrooz; Gorgin, Saeid Redundant-digit floating-point addition scheme based on a stored rounding value. (English) Zbl 1367.65227 IEEE Trans. Comput. 59, No. 5, 694-706 (2010). MSC: 65Y04 × Cite Format Result Cite Review PDF Full Text: DOI
Jaberipur, Ghassem; Parhami, Behrooz; Ghodsi, Mohammad An efficient universal addition scheme for all hybrid-redundant representations with weighted bit-set encoding. (English) Zbl 1104.94067 J. VLSI Signal Process. Syst. Signal Image Video Technol. 42, No. 2, 149-158 (2006). MSC: 94C10 68Q05 94A29 11A63 × Cite Format Result Cite Review PDF Full Text: DOI
Jaberipur, Ghassem; Parhami, Behrooz; Ghodsi, Mohammad Weighted two-valued digit-set encodings: unifying efficient hardware representation schemes for redundant number systems. (English) Zbl 1374.68014 IEEE Trans. Circuits Syst. I, Regul. Pap. 52, No. 7, 1348-1357 (2005). MSC: 68M07 11Y16 × Cite Format Result Cite Review PDF Full Text: DOI