SPEEDY on Cortex-M3: efficient software implementation of SPEEDY on ARM Cortex-M3. (English) Zbl 07628063
Park, Jong Hwan (ed.) et al., Information security and cryptology – ICISC 2021. 24th international conference, Seoul, South Korea, December 1–3, 2021. Revised selected papers. Cham: Springer. Lect. Notes Comput. Sci. 13218, 434-444 (2022).
Summary: The SPEEDY block cipher suite announced at CHES 2021 shows excellent hardware performance. However, SPEEDY was not designed to be efficient in software implementations. SPEEDY’s 6-bit S-box and bit permutation operations generally do not work efficiently in software. We implemented SPEEDY block cipher by applying the implementation technique of bit-slicing. As an implementation technique of bit-slicing, SPEEDY can be operated in software very efficiently and can be applied in microcontroller. By calculating the round key in advance, the performance on ARM Cortex-M3 for SPEEDY-5-192, SPEEDY-6-192, and SPEEDY-7-192 are 65.7, 75.25, and 85.16 clock cycles per byte (i.e. cpb), respectively. It showed better performance than AES-128 constant-time implementation and GIFT constant-time implementation in the same platform. Through this, we conclude that SPEEDY can show good performance on embedded environments.
For the entire collection see [Zbl 1499.68021].
For the entire collection see [Zbl 1499.68021].
References:
| [1] | Leander, G.; Moos, T.; Moradi, A.; Rasoolzadeh, S., The SPEEDY family of block ciphers: engineering an ultra low-latency cipher from gate level for secure processor architectures, IACR Trans. Cryptographic Hardware Embed. Syst., 2021, 510-545 (2021) · doi:10.46586/tches.v2021.i4.510-545 |
| [2] | Reis, TBS; Aranha, DF; López, J.; Fischer, W.; Homma, N., PRESENT runs fast, Cryptographic Hardware and Embedded Systems - CHES 2017, 644-664 (2017), Cham: Springer, Cham · Zbl 1450.94041 · doi:10.1007/978-3-319-66787-4_31 |
| [3] | Adomnicai, A.; Najm, Z.; Peyrin, T., Fixslicing: a new GIFT representation: fast constant-time implementations of GIFT and GIFT-COFB on ARM cortex-M, IACR Trans. Cryptographic Hardware Embed. Syst., 2020, 402-427 (2020) |
| [4] | Schwabe, P.; Stoffelen, K.; Avanzi, R.; Heys, H., All the AES you need on Cortex-M3 and M4, Selected Areas in Cryptography - SAC 2016, 180-194 (2017), Cham: Springer, Cham · Zbl 1412.94209 · doi:10.1007/978-3-319-69453-5_10 |
| [5] | Biham, E.; Biham, E., A fast new DES implementation in software, Fast Software Encryption, 260-272 (1997), Heidelberg: Springer, Heidelberg · Zbl 1385.94014 · doi:10.1007/BFb0052352 |
| [6] | May, L.; Penna, L.; Clark, A.; Dawson, EP; Clark, A.; Boyd, C., An implementation of Bitsliced DES on the Pentium MMX^TM processor, Information Security and Privacy, 112-122 (2000), Heidelberg: Springer, Heidelberg · Zbl 0963.94502 · doi:10.1007/10718964_10 |
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