This is a research monograph on topics related to unreliable logic circuits. There are many reasons which cause that in nowadays’ post-CMOS logic circuits transient faults are unavoidable. Circuits in new nanoscale technologies like carbon nanotubes, resonant tunneling diodes and quantum dots cellular automata are affected by several factors like radiation and neutrons produced by cosmic rays. In the past, circuits were reliable under usual conditions, and those which had to be extremely reliable were built with huge amount of redundancy, like triple modular redundancy (TMR). Designers of present nanoscale logic circuits must take into account the inherent unreliability under normal working conditions and are obliged to use design procedures which allow them to achieve a highly satisfactory level of reliability. It should be noted that not only memory circuits but also logic gates are affected by faults.
The goal of the research presented in this book is to find a more economical approach than TMR to design circuits. The authors formulate an analysis framework which may be useful for analyzing, designing, and testing logic circuits with probabilistic behavior.
In the first, introductory chapter, technology trends that lead to increased uncertainty in circuit behavior are reviewed. Chapter 2 gives the formalism for analyzing circuit reliability using a representation called probabilistic transfer matrix (PTM). A probabilistic transfer matrix gives the probability of each output combination, conditioned upon the input combinations. Matrix and tensor operations are defined and their usage for fault and glitch attenuation modeling is shown. The next chapter deals with compressed forms of probabilistic transfer matrices. Compression using decision diagrams is necessary in order to obtain representations that are more practical and feasible to use. Several heuristics are presented for improving the scalability of PTM-based computations, including dynamic evaluation ordering, partitioning, hierarchical computations, and sampling. Chapter 4 deals with testing logic circuits for probabilistic faults. Testing for probabilistic faults requires repetitions of test patterns and analysis of path dependency since some test vectors detect transient faults with higher probability than others due to masking effects. Chapter 5, entitled “Signature-based reliability analysis”, describes a soft error rate analysis tool called AnSER. It uses simulation based on bit-parallel signal representations called signatures. It allows one to compare the probabilities of fault propagation and the testability of the faults. In Chapter 6 the analysis techniques from the previous chapters are applied to the design of reliable circuits. The following methods are employed – logic rewriting, gate hardening, SiDeR (functional relationships among signals to partially replicate areas of logic with low redundancy). Design for robustness treats also sequential circuits. Gate relocation technique targets timing masking, a factor which has often been overlooked in fault-tolerant design. This technique entails no area overhead and negligible performance overhead. For sequential circuits, integer linear programs are used for retiming. Latches are moved to positions where errors are less likely to propagate to primary outputs.
To conclude, this valuable book summarizes results of the authors’ research in the hot and important topic of building reliable circuits using unreliable components and technologies. It seems that further studies should treat such problems in comparison with other approaches based on Boolean differential calculus, and consider the influence of ageing the system.