This is a 900 pages handbook on Verilog hardware description language. The history of Verilog began in 1985 when it was conceived as proprietary simulation language. The development by the US Department of Defense of the VHSIC language stimulated the industry to open the proprietary solution to public use and extend its features to synthesis procedures. The first Veilog standard was established in 1995 and revisions were made in March 2002 and in 2003. In 2004 the new working group IEEE 1800 was formed with the goal to extend Verilog, but this topic is beyond the scope of this book. The question, which of the two languages – Verilog or VHSIC – is better, is still open. Their use may depend on a designer’s experience – Verilog resembles C-language while VHSIC is Ada-like.
The purpose of this book is to present the complete Verilog language. Verilog supports various modeling constructs at many levels of abstractions – from a logic gate to a complex digital system, and even to a mainframe computer. The book contains a large number of functional blocks descriptions – from counters to RISC processor. Emphasis is placed on the detailed design including the design module, the test bench module, the outputs from the simulator and the waveforms.
There are 11 chapters and 3 appendices in the book. After a short history of HDLs and signal representations in the introductory chapter, basic concepts of modeling techniques – data-flow, behavioral and structural modeling – are presented. Verilog models use modules (basic units of hardware) and ports allowing communication of modules with external environment. Chapter 3 defines Verilog language elements – comments, identifiers, keywords, data types, parameters and logic states. The predefined data types include nets connecting logical elements and registers providing storage elements. The next chapter is devoted to expressions consisting of operands and operators, which are the basis of Verilog HDL. Chapter 5 discusses gate-level modeling using built-in primitives. The description includes gate delays. Chapter 6 shows the ability of designing in Verilog user-defined primitives. They can be used in designing combinational as well as sequential logic circuits. Many design examples are given. Chapter 7 is devoted to dataflow modeling which is higher in level abstraction than either built-in primitives or user-defined primitives. As previously, many design examples are given. Chapter 8 is devoted to behavioral modeling representing higher level of abstraction without internal structure details. A Verilog module that is designed using behavioral modeling contains procedural assignments and different delay techniques. Many complete design examples illustrate this modeling approach. Chapter 9 is devoted to structural modeling consisting of instantiating built-in primitives, user-defined primitives or other design modules into one large design module. As in other chapters many examples are given. Chapter 10 presents tasks and functions resembling procedures or subroutines in programming languages. These constructs allow a behavioral module to be partitioned into smaller segments. Code segments may be written once and called as required. Chapter 11 presents several complex design examples with the complete design of a pipelined RISC processor as final example. At the end of each chapter a series of questions and exercises are formulated.
Three appendices include: event handling using the event queue, a procedure for project implementation, and answers to exercises.
This book presents ready-to-use material for a one or two-semester course on the use of Verilog for digital design and modeling. Background in combinational and sequential logic design is required. The book may also be very valuable for practicing designers of VLSI circuits.