Neural-MOS threshold gate as a way to design on-chip learning neuron structures. (English) Zbl 1040.68010
Kluev, V. V. (ed.) et al., Topics in applied and theoretical mathematics and computer science. Athens: WSEAS Press (ISBN 960-8052-47-6/hbk). Mathematics and Computers in Science and Engineering. A Series of Reference Books and Textbooks, 197-201 (2001).
Summary: Hardware implementation of artificial neuron networks based on MOS-transistors with floating gates (Neuron MOS or vMOS) is discussed. Comparison of two type on-chip learning neurons with digital and analog input weight storing is provided. The main problem in design the neuron with analog input weight memory is tolerance to deviations of circuit elements parameters and supplied voltage deviation. New neuron circuit that can compensate all kind of deviations is proposed and investigated. Design methodology of such a circuit and result of simulation are shown.
For the entire collection see [Zbl 1028.00013].
For the entire collection see [Zbl 1028.00013].
MSC:
| 68M99 | Computer system organization |
| 68T05 | Learning and adaptive systems in artificial intelligence |
