Summary: The Supplementary Symmetrical Logic Circuit (SUS-LOC) structure uses multiple power supply voltages to define multiple logic values. Pass transistor networks provide a path between the output node and the specific power supply needed to provide the desired logic level on the output. For each combination of inputs, there is only one path between the output node and a power source or ground. Thus, the DC power approaches zero as is seen in standard binary CMOS. A test chip fabricated in a standard 1.2-micron CMOS technology demonstrates the operation of a ternary logic function designed using the SUS-LOC structure. Logic functionality and switching performance are verified experimentally. Simulated and experimental switching times are presented and compared.