Summary: Very fast and accurate 3-D capacitance extraction is essential for interconnect optimization in VLSI ultra-deep sub-micron designs. Parallel processing provides an approach to reducing the simulation turn-around time. This paper examines the parallelization of the well-known fast multipole-based 3-D capacitance extraction program FASTCAP, which employs new adaptive and preconditioning techniques. To account for the complicated data dependencies in the unstructured problems, we propose a novel generalized cost function model, which can be used to accurately measure the workload associated with each cube in the hierarchy. We then present two adaptive partitioning schemes, combined with efficient communication mechanisms with bounded buffer size, to reduce the parallel processing overhead. The overall load balance is achieved through balancing the load at each level of the multipole computation. We report detailed performance results on a variety of distributed memory parallel platforms, using standard benchmarks on 3-D capacitance extraction.