This book is a research monograph dealing with the influence of inductance on interconnection path electrical properties in submicron technology integrated circuits. Models of transmission lines taking into account the inductance are used to evaluate errors caused by considering RC only schemes. Such errors have been estimated to reach over 35% of the propagation delay in 0.25 micron CMOS technology. The effects of inductance became more important with usage of less resistive copper interconnect.
The key to achieving the goals stated in this book are appropriate mathematical and simulation models describing precisely interconnection paths in integrated circuits. The book is organized around four threads. The first thread deals with models of interconnections described as electrical high frequency transmission lines. The second thread could be described as CMOS gates driving characteristics. The third one concerns optimization of repeater insertion. In the fourth, the authors analyse how inductance may positively influence transient response properties and enhance the design optimality.
On-chip interconnections as transmission lines: The basic theory is formulated in the time domain. Three types of transmission lines, lossless (LC), lossy (RLC), and RC, are taken into consideration. Transient responses for three different source impedances, large, matched and small, are evaluated. However the analysis in the time domain is limited, therefore the majority of results is obtained using transformations. Historically, these methods evolve from Elmore delay and Wyatt’s approximation for RC tree extended further for RLC trees. These methods calculate the propagation delay of a multi-pole system for a step input, given the transfer function of a system. The common method for more accurate transient response calculation for RLC interconnects are moment matching techniques. However, the methods mentioned have numerical and computational issues like unstable poles, numerical precision, or errors due to truncation time of computation. Numerical methods have been compared to simulation results from dynamic simulators like SPICE and mainly AS/X (AS/X is used by IBM). As a generalization of the Elmore delay model for RLC trees or zigzag lines, the second order approximation is applied. Line characteristics like branching factor, depth and node position are taken into account. As usual in this book, the analytical expressions are compared to results from AS/X simulations. The authors attempt to use the most suitable engineering calculations, based on such criteria as accuracy, stability, computational speed, culminates in the DTT (direct truncation of the transfer function) method. Advantages over moment matching techniques are pointed out.
CMOS gate driving characteristics: A closed form solution for the output signal of a CMOS inverter driving an RLC transmission line is formulated. It is based on the alpha power law for deep submicrometer technologies. Two figures of merit useful for determining if a section of interconnect should be modeled as either an RLC or an RC impedance are presented, the damping factor, and the ratio of the rise time of the input signal at the driver of an interconnect line to the time of flight of the signals across the line. These two figures of merit can be combined on a condition that determines the range of the length of interconnect in which inductance effects are significant. This formula gives consistent results with AS/X simulations. As a limiting case, the lossless transmission line is considered.
Repeater insertion: One of the important design issues is optimal repeater insertion. Considering RLC models of transmission lines instead of the RC model may improve the overall repeater solution by 40% in terms of area, 15% in terms of power and 7% in terms of signal delay.
More optimal design with effects of inductance: It is shown that inductance improves the signal slew rate, reduces significantly the short-circuit power consumption and reduces the area of the active repeaters inserted to optimize the performance of long interconnects.
Conclusions: It seems that the importance of taking the on-chip inductance grows with higher frequencies and smaller geometry. The analysis techniques presented in this book may be of interest to designers of gigahertz IC as well as for researchers in the area of high frequency interconnections.