This book is devoted to methodology of designing low power digital circuits. Low power dissipation is becoming very important constraint in designing VLSI circuits. Increase in VLSI circuit complexity and higher timing frequencies lead to higher power consumption, causing excessive heat dissipation. In portable systems battery life shortens. The first part of the book reviews the power estimation methods. These methods are subsequently utilized as a means of comparing different implementations of the same system in the second part of the book. Power estimation methods (exact and probabilistic) have been reviewed for combinational and sequential logic circuits. The average power dissipation is directly related to the average switching activity, i.e. the quantity and frequency of state transitions. Power estimation in combinational circuits is based on a technique of symbolic simulation. A variable delay model is used which correctly computes the Boolean conditions that cause glitching (i.e. multiple transitions at a gate). It allows to compute the probability of each gate switching at any particular time point. These probabilities are then summed over all gates. The application of this method to sequential circuits requires take into account the correlation between the logic values for consecutive clock cycles. State probabilities are computed using the Chapman-Kolmogorov equations, and present state line probabilities are computed by solving a system of nonlinear equations.
The book presents two optimization techniques for low power circuits at the logic level. The optimization does not consider technological aspects such as changing the clock frequency and/or power supply voltage. First technique – retiming – consists in repositioning the registers in a sequential circuit, while maintaining its external functional behavior. Retiming aims at reducing glitching in the circuit. It is observed that the switching activity at the output of a register can be significantly less than at the register’s input (glitching in the input signal is filtered by the register). It is shown that retiming can result in up to 16% power reduction, however – the applicability of this method is limited to pipelined circuits. Second technique – precomputational – is based on selectively precomputing the output logic values of the circuit one clock before they are required and using the precomputed values to reduce internal switching activity in the succeeding clock cycle. Since precomputation requires additional circuitry and computation, it is reasonable to decide whether the precomputation logic should be applied to all input variables or to only a subset of input variables. In the final chapter of the book the power reduction on the higher levels of abstraction (behavioral, RT) is discussed. It is pointed out that it is difficult to evaluate power consumption at higher than logic levels.