This dissertation elaborated at Universität-Gesamthochschule Siegen deals with partitioning of logic circuits in order to enhance their testability. The partitioning allows to limit the overall length of test patterns as well as time of carrying on the testing procedure. The presented partitioning methods concerns mainly combinational circuits. They can be separated in digital systems from the storage components by the known scan-path-method. The partitioning algorithm is based on the cluster analysis technique taking into account controllability/Observability measures for the logic circuits. Such measures are assumed after ?. Goldstein [Controllability/Observability analysis of digital circuits, IEEE Trans. Circuits Syst. CAS-26, 685-693 (1979)]. Each node in the circuit is characterized by a numerical 3-tuple \((CC^ 0,CC^ 1,CO)\), where \(CC^ 0\) is the 0-controllability, \(CC^ 1\) is the 1-controllability and CO is the observability. The controllability is defined as the minimal number of nodes in the circuit, to which the fixed logical values must be assigned in order to define the value of the considered node. On the other hand, the observability is the minimal expenditure which is necessary to carry the required logical value from the considered node to the actual output of the circuit. Cluster building begins from considering the basic gates as primary clusters and proceeds with grouping the gates into more complex clusters. After forming new clusters, the new values of 3-tuples are examined, if their values exceeds the preassigned ones. If not, the clusters grow step-by-step, if so - cluster building is finished and the necessary connections between clusters are defined. It should be noted that the testability analysis is now used in several software products like SCOAP, CAMELOT, COMET and VICTOR (some are commercially available). The book is written in an informal, descriptive way and is easy readable.