A class of systolic multiplier units for VLSI technology. (English) Zbl 0591.94033
The architecture of a new systolic multiplier unit is introduced, and the VLSI design of this architecture is given. The proposed multiplication algorithm views the numbers as a string of bits, thus eliminating the need for any adder in the design. The main advantages of the proposed architecture are the following two: 1) the regularity of data flow through the system providing a suitable ground for the current VLSI technology, 2) the reduction of required I/O PINs per chip by a factor of two in the comparison with alternative models.
Reviewer: J.Hromkovič
MSC:
| 94C10 | Switching theory, application of Boolean algebra; Boolean functions (MSC2010) |
| 94C30 | Applications of design theory to circuits and networks |
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