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Thulasiraman, K.; Swamy, M. N. S.; Reddy, P. S.

(n+p)-node realizability of Y-matrices of (n+1)-node resistance n-port networks. (English) Zbl 0391.94021

Int. J. Circuit Theory Appl. 6, 253-263 (1978).
Page: −5 −4 −3 −2 −1 ±0 +1 +2 +3 +4 Show Scanned Page
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MSC:

94C05 Analytic circuit theory

Keywords:

(N+Tp)-Node Realizability; Short Circuit Admittace Matrices; (N+1)-Node Passive Linear Resistive N-Port Networks
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References:

[1] Prigozy, IEEE Trans. Circuits and Systems CAS-23 pp 129– (1976)
[2] and , ’(N + 2)-node resistive n-port realizability of Y-matrices’, presented at the IEEE Int. Symp. on Circuits and Systems, Boston, April 1975, and accepted for publication in IEEE Trans. Circuits and Systems.
[3] Lempel, IEEE Trans. Circuitzry CT-15 pp 50– (1968)
[4] Reddy, IEEE Trans. Circuit Theory CT-17 pp 475– (1970)
[5] Murti, IEEE Trans. Circuit Theory CT-15 pp 54– (1968)
[6] Thulasiraman, Proc. IEE 115 pp 1269– (1968)
[7] Guillemin, IRE Trans. Circuit Theory CT-7 pp 303– (1960) · doi:10.1109/TCT.1960.1086676
[8] and , ’Analysis and synthesis of K- and Y-matrices of resistive n-port networks’, Asilomar Conference on Circuits and Systems Theory, Monterey, California, U.S.A., Nov. 1971.
[9] Network Analysis and Synthesis, McGraw-Hill, New York, 1962. · Zbl 0119.22301
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