I'm working on homework for computer architecture and can't understand the premise of the exercise

Question

I'm working on problem 8.6 from the book "Computer organization and embedded systems, 6th edition" and I'm struggling with understanding the setup of the problem. I've taken a screenshot of the problem and posted it below:

I'm having difficulties understanding the functionality of the cache. The problem statement specifies the cache as "small for illustrative purposes" and that "It contains only four 16-bit words". As I understand it the cache literally only contains these 4 slots for word-length data or instructions. Furthermore the cache is direct-mapped so instructions/data loaded into it should be placed into it by their "main-memory address" modulo "number of blocks in the cache". Now the cache only has four blocks (which aren't even blocks) so it's just "memory address" modulo 4? That seem ridiculous. Another problem I have is that "Words are accessed in the cache using the low-order 3 bits of an address". I don't even know how that would work with the tag saved in the cache, or rather what is the purpose of the tag then since there are only 4 places in the cache.

English is not my first language so I'm afraid that maybe there are nuances in the specification I don't fully understand but either way I can't make heads or tails of it.

Answer 1

You are right about the cache. It can just cache 4 words(each word is 2 bytes), and it just use the address module 8(That is what a direct mapped cache is).

This might seem really small, but if you for example look at a 68020 cpu, it only used "256 byte direct-mapped instruction cache, arranged as 64 four-byte entries" so small caches are not that odd. (I think they made it so small, so you would be able to follow its content by hand. You don't even want to try to show/calculate a modern 2MB cache by hand).

Since an address is stored module 8, you only need the lowest 3 bits of an address, in order to get its slot position in the cache.

(Added that the address is stored module 8, and not module 4, because each word in the cache is 2 bytes, and not 1).

The purpose of the tag, is to verify that the value in the cache, is the value in the address you request.

Example: You write 0xffff to address 2+3, and this is stored in the cache, at position 2.

Now you try to read address 10. Should you use the value in the cache? If address 10 is stored in the cache, it will be stored at cache position 2. But we know that the value stored in cache position 2 is for address 2 and not for address 10, so your read for address 10 must read from the real ram, and not from the cache.

In order to know this, each time the cpu write to the cache, it store the upper 13 bits, and this is called the tag. So each slot in the cache, contains 16 bit for the value stored at the cache position, together with a 13 bit tag.

That way it can compare the tag, with the address you want to read, and then know if it should use the cache value, or read from the ram.