research-article

A case for integrated processor-cache partitioning in chip multiprocessors

Authors:

Shekhar Srikantaiah,

Reetuparna Das,

Asit K. Mishra,

Mahmut KandemirAuthors Info & Claims

SC '09: Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis

Article No.: 6, Pages 1 - 12

https://doi.org/10.1145/1654059.1654066

Published: 14 November 2009 Publication History

Abstract

Existing cache partitioning schemes are designed in a manner oblivious to the implicit processor partitioning enforced by the operating system. This paper examines an operating system directed integrated processor-cache partitioning scheme that partitions both the available processors and the shared cache in a chip multiprocessor among different multi-threaded applications. Extensive simulations using a set of multiprogrammed workloads show that our integrated processor-cache partitioning scheme facilitates achieving better performance isolation as compared to state of the art hardware/software based solutions. Specifically, our integrated processor-cache partitioning approach performs, on an average, 20.83% and 14.14% better than equal partitioning and the implicit partitioning enforced by the underlying operating system, respectively, on the fair speedup metric on an 8 core system. We also compare our approach to processor partitioning alone and a state-of-the-art cache partitioning scheme and our scheme fares 8.21% and 9.19% better than these schemes on a 16 core system.

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Cited By

Kundan SMarinakis TAnagnostopoulos IKagaris D(2022)A Pressure-Aware Policy for Contention Minimization on Multicore SystemsACM Transactions on Architecture and Code Optimization10.1145/352461619:3(1-26)Online publication date: 25-May-2022
https://dl.acm.org/doi/10.1145/3524616
Salami BNoori HNaghibzadeh M(2022)Online energy-efficient fair scheduling for heterogeneous multi-cores considering shared resource contentionThe Journal of Supercomputing10.1007/s11227-021-04159-878:6(7729-7748)Online publication date: 3-Jan-2022
https://doi.org/10.1007/s11227-021-04159-8
Patel TTiwari D(2020)CLITE: Efficient and QoS-Aware Co-Location of Multiple Latency-Critical Jobs for Warehouse Scale Computers2020 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA47549.2020.00025(193-206)Online publication date: Feb-2020
https://doi.org/10.1109/HPCA47549.2020.00025
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Index Terms

A case for integrated processor-cache partitioning in chip multiprocessors
1. Hardware
  1. Hardware validation
  2. Integrated circuits
    1. Semiconductor memory
      1. Dynamic memory

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cover image ACM Conferences

SC '09: Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis

November 2009

778 pages

ISBN:9781605587448

DOI:10.1145/1654059

Conference Chair:
Wilfred Pinfold

Copyright © 2009 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 14 November 2009

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SC '09: International Conference for High Performance Computing, Networking, Storage and Analysis

November 14 - 20, 2009

Oregon, Portland

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SC '09 Paper Acceptance Rate 59 of 261 submissions, 23%;

Overall Acceptance Rate 1,516 of 6,373 submissions, 24%

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Cited By

Kundan SMarinakis TAnagnostopoulos IKagaris D(2022)A Pressure-Aware Policy for Contention Minimization on Multicore SystemsACM Transactions on Architecture and Code Optimization10.1145/352461619:3(1-26)Online publication date: 25-May-2022
https://dl.acm.org/doi/10.1145/3524616
Salami BNoori HNaghibzadeh M(2022)Online energy-efficient fair scheduling for heterogeneous multi-cores considering shared resource contentionThe Journal of Supercomputing10.1007/s11227-021-04159-878:6(7729-7748)Online publication date: 3-Jan-2022
https://doi.org/10.1007/s11227-021-04159-8
Patel TTiwari D(2020)CLITE: Efficient and QoS-Aware Co-Location of Multiple Latency-Critical Jobs for Warehouse Scale Computers2020 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA47549.2020.00025(193-206)Online publication date: Feb-2020
https://doi.org/10.1109/HPCA47549.2020.00025
Raveendran ASherly E(2019)TAR Based Hotspot Prediction in Cloud Data CentresInternational Journal of Grid and High Performance Computing10.4018/IJGHPC.201907010111:3(1-22)Online publication date: Jul-2019
https://doi.org/10.4018/IJGHPC.2019070101
Hua YLiu XHua YLiu X(2019)Data Similarity-Aware Computation Infrastructure for the CloudSearchable Storage in Cloud Computing10.1007/978-981-13-2721-6_7(153-178)Online publication date: 9-Feb-2019
https://doi.org/10.1007/978-981-13-2721-6_7
Mittal S(2017)A Survey of Techniques for Cache Partitioning in Multicore ProcessorsACM Computing Surveys10.1145/306239450:2(1-39)Online publication date: 10-May-2017
https://dl.acm.org/doi/10.1145/3062394
Zhao JCui HXue JFeng X(2016)Predicting Cross-Core Performance Interference on Multicore Processors with Regression AnalysisIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2015.244298327:5(1443-1456)Online publication date: 1-May-2016
https://dl.acm.org/doi/10.1109/TPDS.2015.2442983
Herdrich AVerplanke EAutee PIllikkal RGianos CSinghal RIyer R(2016)Cache QoS: From concept to reality in the Intel® Xeon® processor E5-2600 v3 product family2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2016.7446102(657-668)Online publication date: Mar-2016
https://doi.org/10.1109/HPCA.2016.7446102
Beckmann NSanchez D(2016)Modeling cache performance beyond LRU2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2016.7446067(225-236)Online publication date: Mar-2016
https://doi.org/10.1109/HPCA.2016.7446067
Beckmann NSanchez D(2015)Talus: A simple way to remove cliffs in cache performance2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2015.7056022(64-75)Online publication date: Feb-2015
https://doi.org/10.1109/HPCA.2015.7056022
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