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A Low-power 4096x2160@30fps H.265/HEVC Video Encoder for Smart Video Surveillance

Published: 23 July 2018 Publication History

Abstract

This paper presents the design and VLSI implementation of a low-power HEVC main profile encoder, which is able to process up to 4096x2160@30fps 4:2:0 encoding in real-time with five-stage pipeline architecture. A pyramid ME (Motion Estimation) engine is employed to reduce search complexity. To compensate for the video sequences with fast moving objects, GME (Global Motion Estimation) are introduced to alleviate the effect of limited search range. We also implement an alternative 5x5 search along with 3x3 to boost video quality. For intra mode decision, original pixels, instead of reconstructed ones are used to reduce pipeline stall. The encoder supports DVFS (Dynamic Voltage and Frequency Scaling) and features three operating modes, which helps to reduce power consumption by 25%. Scalable quality that trades encoding quality for power by reducing size of search range and intra prediction candidates, achieves 11.4% power reduction with 3.5% quality degradation. Furthermore, a lossless frame buffer compression is proposed which reduced DDR bandwidth by 49.1% and power consumption by 13.6%. The entire video surveillance SoC is fabricated with TSMC 28nm technology with 1.96 mm2 area. It consumes 2.88M logic gates and 117KB SRAM. The measured power consumption is 103mW at 350MHz for 4K encoding with high-quality mode. The 0.39nJ/pixel of energy efficiency of this work, which achieves 42% ~ 97% power reduction as compared with reference designs, make it ideal for real-time low-power smart video surveillance applications.

References

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G.J. Sullivan, J. Ohm, Woo-Jin Han, and T. Wiegand. 2012. Overview of the high efficiency video coding (HEVC) standard. IEEE Transactions on Circuits and Systems for Video Technology, vol. 22, no. 12, 1649--1668, Dec 2012.
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F. Bossen, B. Bross, K. Suhring, and D. Flynn. 2012. HEVC complexity and implementation analysis. IEEE Transactions on Circuits and Systems for Video Technology, vol. 22, no. 12, 1685--1696, Dec 2012.
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K. Xu, C. S. Choy. 2007. Low-power H.264/AVC baseline decoder for portable applications. ACM/IEEE International Symposium on Low Power Electronics and Design, 256--261, 2007.
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J. Guo, and M. Potkonjak. 2016. Coarse-grained learning-based dynamic voltage frequency scaling for video decoding. 26th International Workshop on PATMOS, 84--91, 2016.
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Cited By

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  • (2022)Image and Video Coding Techniques for Ultra-low LatencyACM Computing Surveys10.1145/351234254:11s(1-35)Online publication date: 9-Sep-2022
  • (2022)High-Level Synthesis Implementation of an Embedded Real-Time HEVC Intra Encoder on FPGA for Media ApplicationsACM Transactions on Design Automation of Electronic Systems10.1145/349121527:4(1-34)Online publication date: 8-Mar-2022
  • (2022)Releasing the Memory Bottleneck to Display Video Correctly2022 19th International SoC Design Conference (ISOCC)10.1109/ISOCC56007.2022.10031379(340-341)Online publication date: 19-Oct-2022
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  1. A Low-power 4096x2160@30fps H.265/HEVC Video Encoder for Smart Video Surveillance

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    Published In

    cover image ACM Conferences
    ISLPED '18: Proceedings of the International Symposium on Low Power Electronics and Design
    July 2018
    327 pages
    ISBN:9781450357043
    DOI:10.1145/3218603
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 23 July 2018

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    Author Tags

    1. Bandwidth compression
    2. DVFS
    3. HEVC
    4. encoder
    5. low-power

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    Overall Acceptance Rate 398 of 1,159 submissions, 34%

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    Cited By

    View all
    • (2022)Image and Video Coding Techniques for Ultra-low LatencyACM Computing Surveys10.1145/351234254:11s(1-35)Online publication date: 9-Sep-2022
    • (2022)High-Level Synthesis Implementation of an Embedded Real-Time HEVC Intra Encoder on FPGA for Media ApplicationsACM Transactions on Design Automation of Electronic Systems10.1145/349121527:4(1-34)Online publication date: 8-Mar-2022
    • (2022)Releasing the Memory Bottleneck to Display Video Correctly2022 19th International SoC Design Conference (ISOCC)10.1109/ISOCC56007.2022.10031379(340-341)Online publication date: 19-Oct-2022
    • (2019)A 4K Vision Computing Platform with Convolutional Neural Network Engine on FPGA2019 32nd IEEE International System-on-Chip Conference (SOCC)10.1109/SOCC46988.2019.1570552941(171-175)Online publication date: Sep-2019

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