research-article

Evaluation of voltage stacking for near-threshold multicore computing

Authors:

Sae Kyu Lee,

David Brooks,

Gu-Yeon WeiAuthors Info & Claims

ISLPED '12: Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design

Pages 373 - 378

https://doi.org/10.1145/2333660.2333746

Published: 30 July 2012 Publication History

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Abstract

This paper evaluates voltage stacking in the context of near-threshold multicore computing. Key attributes of voltage stacking are investigated using results from a test-chip prototype built in 150nm FDSOI CMOS. By "stacking" logic blocks on top of each other, voltage stacking reduces the chip current draw and simplifies off-chip power delivery but within-die voltage noise due to inter-layer current mismatch is an issue. Results show that unlike conventional power delivery schemes, supply rail impedance in voltage stacked systems depend on aggregate power consumption, leading to better noise immunity for high power (low impedance) operation for many-core processors.

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Cited By

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Chauviere BStevens K(2024)Voltage Stacking: A First-Order Modelization of an m × n Asynchronous Array for Chip and Architectural Design ExplorationJournal of Low Power Electronics and Applications10.3390/jlpea1403004414:3(44)Online publication date: 27-Aug-2024
https://doi.org/10.3390/jlpea14030044
Zhuldassov NXu KFriedman E(2022)Converter Topologies for On-Package Voltage Stacking2022 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS48785.2022.9937679(546-550)Online publication date: 28-May-2022
https://doi.org/10.1109/ISCAS48785.2022.9937679
Zou ALeng JHe XZu YGill CReddi VZhang X(2020)Voltage-Stacked Power Delivery Systems: Reliability, Efficiency, and Power ManagementIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.296960739:12(5142-5155)Online publication date: Dec-2020
https://doi.org/10.1109/TCAD.2020.2969607
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Index Terms

Evaluation of voltage stacking for near-threshold multicore computing
1. Hardware
  1. Very large scale integration design
    1. VLSI system specification and constraints

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Published In

ISLPED '12: Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design

July 2012

438 pages

ISBN:9781450312493

DOI:10.1145/2333660

General Chairs:
Naresh Shanbhag
University of Illinois at Urbana-Champaign, USA
,
Massimo Poncino
Politecnico di Torino, Italy
,
Program Chairs:
Pai H. Chou
University of California, Irvine / NTHU
,
Ajith Amerasekera
Texas Instruments, USA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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Published: 30 July 2012

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ISLPED'12: International Symposium on Low Power Electronics and Design

July 30 - August 1, 2012

California, Redondo Beach, USA

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Chauviere BStevens K(2024)Voltage Stacking: A First-Order Modelization of an m × n Asynchronous Array for Chip and Architectural Design ExplorationJournal of Low Power Electronics and Applications10.3390/jlpea1403004414:3(44)Online publication date: 27-Aug-2024
https://doi.org/10.3390/jlpea14030044
Zhuldassov NXu KFriedman E(2022)Converter Topologies for On-Package Voltage Stacking2022 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS48785.2022.9937679(546-550)Online publication date: 28-May-2022
https://doi.org/10.1109/ISCAS48785.2022.9937679
Zou ALeng JHe XZu YGill CReddi VZhang X(2020)Voltage-Stacked Power Delivery Systems: Reliability, Efficiency, and Power ManagementIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.296960739:12(5142-5155)Online publication date: Dec-2020
https://doi.org/10.1109/TCAD.2020.2969607
Mace JNoh GHa J(2020)Modeling and Design of Switched-Capacitor Converters for Voltage Stacking2020 IEEE 9th International Power Electronics and Motion Control Conference (IPEMC2020-ECCE Asia)10.1109/IPEMC-ECCEAsia48364.2020.9367863(503-510)Online publication date: 29-Nov-2020
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Trapani Possignolo REbrahimi EArdestani ESankaranarayanan ABriz JRenau J(2018)GPU NTC Process Variation Compensation With Voltage StackingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2018.283166526:9(1713-1726)Online publication date: Sep-2018
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Lee STong TZhang XBrooks DWei G(2017)A 16-Core Voltage-Stacked System With Adaptive Clocking and an Integrated Switched-Capacitor DC–DC ConverterIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.263380525:4(1271-1284)Online publication date: 1-Apr-2017
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Fully monolithic cellular buck converter design for 3-D power delivery

Assessing the Impact of Temperature and Supply Voltage Variations in Near-threshold Circuits using an Analytical Model

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