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ORCIDISPD 2018: Monterey, CA, USA
- Chris Chu, Ismail Bustany:
Proceedings of the 2018 International Symposium on Physical Design, ISPD 2018, Monterey, CA, USA, March 25-28, 2018. ACM 2018
Keynote Address
- Anthony M. Hill:
Challenges and Opportunities in Automotive, Industrial, and IoT Physical Design. 1
Finding the Golden Tree in the Forest!
- Andrew B. Kahng, Christopher Moyes, Sriram Venkatesh, Lutong Wang
:
Wot the L: Analysis of Real versus Random Placed Nets, and Implications for Steiner Tree Heuristics. 2-9 - Charles J. Alpert, Wing-Kai Chow, Kwangsoo Han, Andrew B. Kahng, Zhuo Li, Derong Liu, Sriram Venkatesh:
Prim-Dijkstra Revisited: Achieving Superior Timing-driven Routing Trees. 10-17 - Sheng-En David Lin, Dae Hyun Kim:
Construction of All Rectilinear Steiner Minimum Trees on the Hanan Grid. 18-25
FPGA Special Session
- William N. N. Hung, Richard Sun:
Challenges in Large FPGA-based Logic Emulation Systems. 26-33 - Gordon R. Chiu, Andrew C. Ling, Davor Capalija, Andrew Bitar, Mohamed S. Abdelfattah:
Flexibility: FPGAs and CAD in Deep Learning Acceleration. 34-41 - Elliott Delaye, Ashish Sirasao, Ehsan Ghasemi:
Exploration and Tradeoffs of different Kernels in FPGA Deep Learning Applications. 42-47 - S. Alexander Chin, Kuang Ping Niu, Matthew J. P. Walker, Shizhang Yin, Alexander Mertens, Jongeun Lee, Jason Helge Anderson:
Architecture Exploration of Standard-Cell and FPGA-Overlay CGRAs Using the Open-Source CGRA-ME Framework. 48-55
Design Flow and Power Grid Optimization
- Leon Stok:
Concurrent High Performance Processor Design: From Logic to PD in Parallel. 56-57 - André Inácio Reis:
Towards a VLSI Design Flow Based on Logic Computation and Signal Distribution. 58-59 - Wei Ye, Meng Li, Kai Zhong, Bei Yu, David Z. Pan:
Power Grid Reduction by Sparse Convex Optimization. 60-67
Statistical and Machine Learning-Based CAD
- Andrew B. Kahng:
Machine Learning Applications in Physical Design: Recent Results and Directions. 68-73 - Li-C. Wang:
Machine Learning for Feature-Based Analytics. 74-81 - Yibo Lin, Yuki Watanabe, Taiki Kimura, Tetsuaki Matsunawa, Shigeki Nojima, Meng Li, David Z. Pan:
Data Efficient Lithography Modeling with Residual Neural Networks and Transfer Learning. 82-89
Three Shades of Placement!
- Bon Woong Ku, Kyungwook Chang, Sung Kyu Lim:
Compact-2D: A Physical Design Methodology to Build Commercial-Quality Face-to-Face-Bonded 3D ICs. 90-97 - Biying Xu, Bulent Basaran, Ming Su, David Z. Pan:
Analog Placement Constraint Extraction and Exploration with the Application to Layout Retargeting. 98-105 - Wan-Sin Kuo, Shi-Han Zhang, Wai-Kei Mak, Richard Sun, Yoon Kah Leow:
Pin Assignment Optimization for Multi-2.5D FPGA-based Systems. 106-113
Commemoration for Professor Te Chiang Hu
- Andrew B. Kahng:
Influence of Professor T. C. Hu's Works on Fundamental Approaches in Layout. 114-119 - Chung-Kuan Cheng, Ronald L. Graham, Ilgweon Kang, Dongwon Park, Xinyuan Wang:
Tree Structures and Algorithms for Physical Design. 120-125 - Chris Chu:
Pioneer Research on Mathematical Models and Methods for Physical Design. 126-129 - Chung-Kuan Cheng, T. C. Hu, Andrew B. Kahng:
Theory and Algorithms of Physical Design. 130-131
Interconnect Optimization and Detailed Routing Contest Results
- Jiang Hu, Ying Zhou, Yaoguang Wei, Stephen T. Quay, Lakshmi N. Reddy, Gustavo E. Téllez, Gi-Joon Nam:
Interconnect Optimization Considering Multiple Critical Paths. 132-138 - K. Charles Janac:
Interconnect Physical Optimization. 139 - Stefanus Mantik, Gracieli Posser, Wing-Kai Chow, Yixiao Ding, Wen-Hao Liu:
ISPD 2018 Initial Detailed Routing Contest and Benchmarks. 140-143
How to Make Your Foundry Happier?
- Jens Lienig, Matthias Thiele:
The Pressing Need for Electromigration-Aware Physical Design. 144-151 - Alexey Lvov, Gustavo E. Téllez, Gi-Joon Nam:
On Coloring and Colorability Analysis of Integrated Circuits with Triple and Quadruple Patterning Techniques. 152-159 - Raphael Andreoni Camponogara Viera, Jean-Max Dutertre, Philippe Maurine, Rodrigo Possamai Bastos:
Standard CAD Tool-Based Method for Simulation of Laser-Induced Faults in Large-Scale Circuits. 160-167
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