The design of a high-performance processor in an advanced technology node is a highly concurrent process. While most SoCs are designed with (fairly) stable IP, several trends are driving the design of the micro-architecture, the logic and the physical design of high-performance micro-processors to be an increasingly parallel process. Due to the slowdown of technology progress, a lot more innovation is coming from the micro-architecture. Fast evolving workloads lead to frequent additions of accelerators and instructions. Late security findings drive last minute updates. All these have a significant impact on the logic structure of the design and therefore implications to an efficient physical design. On top of that, when designing in an advanced technology, the technology and its design rules are evolving at the same time. High-performance designs have many memories, register files and caches which are especially susceptible to sometimes small technology rule changes. Even a minimal design rule change can percolate up and have a substantial impact on the floorplan. Fortunately, designers have an unprecedented amount of compute power available to them to conquer the challenges outline above and drive a massive concurrent design process. Especially design teams that harness the vast amount of data coming from the concurrent process can efficiently get to their design goals on time.