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Navi, Keivan; Doostaregan, Akbar; Moaiyeri, Mohammad Hossein; Hashemipour, Omid

A hardware-friendly arithmetic method and efficient implementations for designing digital fuzzy adders. (English) Zbl 1238.94042

Fuzzy Sets Syst. 185, No. 1, 111-124 (2011).
Summary: A new hardware-friendly mathematical method for realizing low-complexity universal Adder cells as well as its efficient hardware implementations is proposed in this paper. This method can be used in binary logic, Multiple-Valued Logic (MVL) and specifically digital fuzzy systems. The proposed mathematical method can be implemented in both voltage and current modes. The voltage-mode hardware implementation is very simple and is based on input capacitors and MVL or analog inverters and buffers. In addition, the current-mode hardware implementation leads to simple and efficient structures for digital fuzzy systems. Simulations are carried out for ternary logic as well as for digital fuzzy logic with high precision by using 180 nm standard CMOS technology and at 1.8 V supply voltage. Simulation results demonstrate that the proposed designs have excellent functionality and are very suitable for implementing MVL and fuzzy arithmetic circuits.

Cited in 1 Document

MSC:

94C10 Switching theory, application of Boolean algebra; Boolean functions (MSC2010)
94D05 Fuzzy sets and logic (in connection with information, communication, or circuits theory)

Keywords:

full adder; digital fuzzy sets; fuzzy hardware; multiple-valued logic (MVL); radix-\(r\)
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References:

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