This is a research monograph treating mapping of applications, typically written in high-level imperative programming languages, such as C or MATLAB, to efficient reconfigurable hardware architecture consisting of multiple processing elements and storage structures. The results of such mappings could allow to respond to specific domain requirements such as input data rates or stringent real-time constraints. Although this research domain is far from mature now, many research efforts have been made and they are described in this book.
The book consists of 7 chapters. After a short introduction, reconfigurable architectures are reviewed, and early works by authors such as Estrin, Miller, Cocker, Reddick and Feustel and companies like Altera and Xilinx are quoted. Key characteristics of reconfigurable architectures are discussed. Granularity is one of the key aspects that differentiate reconfigurable architectures: 4mm

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In fine-grained architectures the configurable cells include logic gates, thus allowing the implementation of arbitrary and specialized data-path hardware designs,

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in coarse-grained architectures the configurable cells, often designated as Field-Programmable ALU Arrays (FPAAs), include ALUs and distributed memories,

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in mix-coarse grained architectures the configurable cells include microprocessor cores combined with very fine-grained reconfigurable logic.

The three subsequent chapters present phases of the overall compilation process in the following sequence: 4mm

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At first generic compilation and synthesis flow is discussed. The compiler must not only take into account known instruction set architecture, but also synthesize an application-specific architecture implemented with reconfigurable hardware resources. Moreover, compilers must deal with the many aspects of compilation techniques for parallel computing, like processor synchronization, data partitioning and code generation. The program code resulting after this phase of compilation is not optimal – therefore the next phase is code optimization.

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Code transformations may be deployed at bit level (bit-width narrowing, conversion between floating-point and fixed-point data format), at instruction level (operator strength and height reduction) or at loop-level (loop tiling, loop strip-mining, loop merging). Transformations may be data-oriented or function-oriented. An attempt is made to give advice which code transformation is to be chosen.

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Mapping and execution optimizations are reviewed. The complexity of this problem is increased as compared with traditional architectures by the spatial nature of reconfigurable architectures. Compilers must judiciously balance the use of different kinds of resources in space and time. Very important here is loop pipelining.

In the 6th chapter, plenty of compilers for reconfigurable architectures are compared. The book distinguishes between compilers for fine-grained reconfigurable devices and coarse-grained architectures. Several compilers in each group are shortly characterized and a table comparison is included. Chapter 7 discusses perspectives on programming reconfigurable computing platforms. The book contains 350 items in its bibliography.
The authors finish the book with the following statements: “We believe compilation techniques for reconfigurable computing platforms offer many exciting research and development opportunities. We hope this book, to our knowledge the first book completely dedicated to the topic of compilation for reconfigurable architectures, will motivate further research efforts in this domain and serve as a base for a deeper understanding of the overall compilation and synthesis problems, current solutions, and open issues.”