This book gives an overview of a large spectrum of hardware implementations for computational intelligence. Design concepts are elaborated on the basis of fuzzy logic, genetic algorithms, and neural networks.
The volume is divided into four parts. Part 1 – devoted to evolvable hardware and genetic algorithms – consists of two chapters. Chapter 1 presents automated design synthesis and partitioning for adaptive reconfigurable hardware. The goal is to do the hardware adaptation according to a task formulated in high-level synthesis. Partitioning techniques playing key role in this task are comprehensively reviewed. As an example an arbiter circuit is used. The second chapter analyses hardware implementations of genetic algorithms. A pipelined genetic algorithm processor generates one new, evaluated chromosome per machine cycle. The functions of parent selection, crossover, mutation, evaluation and survival are implemented in hardware in such a manner that each function can be executed in a single machine cycle.
Part 2 of the volume deals with implementations of fuzzy logic processors. A fuzzy processor is an integrated circuit performing complete fuzzy computations, including premise, rule and conclusion evaluation, defuzzification, and rule based memory interface. Chapter 3 presents an introductory overview of several issues related to the implementation of fuzzy logic systems and neural networks. The author emphasizes the hardware specifications issues specific to intelligent systems – architectural, technological and performance specifications are discussed. Various VLSI digital and analog implementations of intelligent systems are reviewed. In chapter 4 methodologies for developing both general purpose and task oriented hardware architectures are covered. Limitations of VLSI implementation caused some simplifications in the architecture of the fuzzy processor. This architecture has been validated by simulations of radar tracking application which are presented. In chapter 5 two versions of a digital fuzzy processor for fuzzy-rule-based systems are described. The hardware implementation issues are discussed in detail and implementation results are presented.
Part 3 of the volume is devoted to neural networks hardware implementations. In chapter 6 the application of the mean field annealing neural networks for optimum multiuser detection for code-division multiple access systems is addressed and the analog VLSI hardware implementation of the application is discussed. The processor is designed for the problem of detecting a spread-spectrum signal in a multiuser channel of wireless mobile communication. Chapter 7 describes analog chip hosting a self-learning neural network. Simulation results on handwritten character recognition are described. In chapter 8 implementation of the pRAM as a VLSI processor incorporating 256 neurons with on-chip learning with the capability of interconnection to form larger networks is described.
In Part 4 parallel and deterministic algorithm for finding subgraph isomorhpisms from a database of attributed, directed model graphs to an attributed, directed input graph is presented. The algorithm utilizes a combination of search networks and tree search to achieve a high-level of parallelism and is especially suited to hierarchically structured interconnection network.
The volume presents state-of-the-art and developments on the leading edge of cognitive science and technology. The clear and concise explanations help the reader to understand the hardware implementation aspects of the new computational intelligence paradigms.
The importance of the implementations for computational intelligence is clearly demonstrated in the book. Plenty of application fields – from biometric image processing, character recognition, object identification through radar tracking, spread spectrum communication, physics experiments, biological neurotransmitter models to high speed networking – have influenced the architectures of implementations. This volume may have significant educational value. Additional teaching material may be obtained from the editor.