This book reviews memory design techniques characterized by low power consumption in embedded processor systems. The saving of energy is of special importance in appliances powered by batteries like cellphones, notebooks, controllers etc. The load of battery is not the only important aspect. The other is the limit of heat generated by system-on-chip because it has influence on the economy of packages. This book considers the low-energy memory problem from the system level point-of-view. The prerequisities for the construction of special memories is some knowledge about the software what allows to predict the access patterns to the memory in the embedded systems. the approach in general-purpose systems is to dynamically reconfigure the memory architecture.
The solutions presented in the book try to answer the following questions:
(1) how to recognize the most frequently accessed memory locations in order to place them near the processor (this organization differs from typical cache),
(2) how to partition the memory into blocks (also taking the dynamic execution profile into account) optimally fitted to execution profile,
(3) how to reduce the memory bandwidth usage by compressing the most commonly executed instructions.
The first chapters of the book are of introductory character. Current System-on-Chip (SoC) design trends are reviewed. System-level design technique background is comprehensively discussed from various points of view. Several real-life systems that are suitable for the application of custom memory architectures – emotion engine, MPEG4 video telephony, and voice recorder are described. Techniques for the design of low-energy memory architectures that have been developed in recent years, and which represent the starting point of the solutions presented afterwards are surveyed. Three main design alternatives are as follows: Application Specific Memories (ASM), memory partitioning, code compression.
Application specific memories. This concept stems from scratch-pad buffer. It is shown that cache memories are flexible due to greater energy cost. The ASM climinates tags logic used in cache by creating application specific decoding logic synthesized at design time. The energy saving in ASM is evidenced using benchmarks.
Memory partitioning. This solution aims at synthesizing multi-banked static RAM on the chip which optimally fits to dynamic execution profile. The recursive memory partitioning algorithm is described. Trade-offs between reduction of energy-per-access due to smaller banks, and increasing of energy by duplicating addressing/control logic and communication resources in the case of multiple banks are outlined. In order to use practically the algorithm it is desirable to link design tools – for partitioning and physical layout. The algorithm has been implemented in CAD tools. Energy saving taking physical layout account is evidenced.
Code compression. Small amount of code executed may be compressed what reduces the amount of memory traffic. It is shown that although additional compression/decompression logic is necessary energy saving may be achieved. As previously practical computations are quoted.
The volume contains rich bibliography (150 items) of the subject. This book is an excellent reference for chip designers, as well as for CAD researchers and developers. The presented methods may be used in CAD systems.