This book addresses many challenging topics related to the Networks-on-Chips research area. Networks-on-Chips (NoC) is an approach to design the communication subsystem of System-on-a-Chip (SoC), usually accommodating multiple asynchronous clocking. NoC brings networking methods to on-chip intercore communication and is characterized by the layered-stack approach. Although NoCs can borrow concepts and techniques from the well-established domain of computer networking, it is not feasible and practical to blindly reuse properties of computer networks and symmetric multiprocessors. Therefore, what are the differences? NoC switches should be small, energy-efficient and fast. The routing algorithms should be implemented by simple logic, and the number of data buffers should be minimal.
The book consists of 11 chapters written by different authors. Ten chapters are written by authors from European research centres, one – on energy and electrical power issues – by authors from the University of California. Each chapter, except the two last ones on industrial design platforms, is in fact a short research monograph on a specific topic.
The book starts by studying 3-dimensional NoC architectures, taking into account consumed energy, information packet latency, and chip area overhead. The results of simulation experiments lead to the conclusion that full 3D structures are not optimal. The goal of the proposed methodology is to find heterogeneous topologies consisting of a mix of 2- and 3-dimensional routers that performs best to the incoming traffic. The next chapter discusses resource allocation schemes that provide shared NoC communication resources. The performance measures are delay, throughput and jitter. Three main categories of resource allocation techniques are considered: circuit switching, time-division multiplexing and aggregate resource allocation. An example of a complex telecom system is given. Chapter 3 deals with NoC communication protocol issues such as switching, routing and flow control. They affect the network throughput, amount of implemented hardware, energy consumption and reliability. Although the discussed techniques stem historically from parallel computers, they have to take into account distinctive concepts for NoCs, namely lossless, low-latency and lightweight network architectures. This chapter surveys the trends in protocols used in commercial and prototype NoC systems. Chapter 4 investigates on-chip processor traffic modelling to evaluate NoC performance. This chapter starts with the background of stochastic processes modelling on-chip processor traffic. Next, the steps involved in the design of a traffic generation environment are discussed. Chapter 5 discusses NoC security issues. Security threats and attacks that could exploit weaknesses in the implementation of a communication infrastructure are outlined. Chapter 6 is devoted to the validation of communication in on-chip networks with emphasis on the application of formal methods. The authors formalize two dimensions of the NoC design space: the communication infrastructure and the communication paradigm as a functional model in the ACL2 logic. ACL2 (A Computational Logic for Applicative Common Lisp) supports automated reasoning in inductive logical theories, mostly for the purpose of software and hardware verification. For each essential design decision – topology, routing algorithm and scheduling policy – a meta-model is given. To ensure correct message delivery on a particular NoC design, one has to instantiate the meta-model with the specific topology, routing and scheduling, and demonstrate that each one of these main instantiated functions satisfies the expected properties and constraints. Chapter 7 studies test and fault tolerance of NoC infrastructures. Of special interest are requirements for test procedures exceeding classical testing of ICs. Faults in the communication subsystem such as crosstalk, packet misrouting and data scrambling must be taken into account in order to provide the integrity of the communication infrastructure. A remedy is provided by novel error-correcting codes. Chapter 8 adapts the concepts of network monitoring to NoC structures. The chapter details the objectives and opportunities of network monitoring and the required interfaces to extract the information from the distributed monitor points. A case study is presented. Chapters 9 covers energy and power issues. This chapter introduces power modeling technologies which are capable of providing a cycle accurate power profile and enable power exploration at the system level. Chapter 10 presents CHAINworks – a suite of software tools from Silistix company. CHAINworks consists of three parts – architect, compiler and library. CHAINworks uses self-timed NoCs to achieve a top-level asynchrony between endpoint blocks as was pointed out by the International Technology Roadmap for Semiconductors. The last chapter presents a platform using Arteris NoC, dedicated to high-performance video applications design. The platform is designed to be flexible, allowing easy implementation of different multimedia applications and scalable to the future evolutions of video encoding standards and mobile applications.
To conclude, many topics related to the implementation of Networks-on-Chips in VLSI technology are covered in this book. The balance between theory and practice of NoC-based systems should be emphasized. The readers are guided through many phases of system design explained reader-friendly. This book may be strongly recommended for professionals as well as lecturers and students of academic courses on design of specialized VLSI implementations.