This volume is a selection of papers from 3 international conferences on computer hardware description languages: 1) Forum on Design Languages (FDL) 2000 in Tübingen (Germany), 2) Annual Intl. Hardware Description Languages Conference and Exhibition (HDLCON) 2000 in Silicon Valley (California), 3) Asia Pacific Chip Design Language (APChDL) 2000 in Beijing (China). The volume comprises 28 papers covering such topics as design methods, specification and modeling languages, tool issues, formal verification, simulation and synthesis. The papers have been grouped into 6 sections. Usually a good habit is to include short introduction to conference session written as a rule by the session chairman. This is not the case here supposedly because the papers have been selected from different conferences by topics and not by conference place and the volume has been not elaborated as a whole. This is a slight drawback of this edition. Sections will be shortly characterized.
VHDL language and its development (5 papers). First paper describes the results of user survey (project funded by U.S. Air Force) carried on in order to identifying the requirements for the next update to VHDL. Variety of language capabilities and features has been taken into account. Till now the first phase of survey has been done. Second phase, based on interviews with chosen respondents is planned for the future. The remaining papers deal with the design quality and mixed level and mixed technology simulation. In order to assess the design quality ARDID – a VHDL quality analysis tool has been developed. It may test a variety of design features and lead to conclusions about quality through simulation of simplified models derived from VHDL descriptions. Next paper considers mixed approach to models, which takes into account abstraction level simulation and behavioral synthesis. Further mixed language simulation environment using languages VHDL, JAVA, and C++ is presented. The environment is based upon an existing VHDL simulator that was extended by open object-oriented JAVA and C++ interfaces. Last paper in this section present state-of-the-art and future predictions for mixed signal (digital and analog) synthesis.
Formal verification (4 papers). In the first paper a theorem prover ACL2 is used to model an abstract behavioral VHDL description. Formal semantic definition of a synthesizable VHDL subset remains readable, is executable and automatically produces all the basic useful theorems that will ease the formal proof of the functional correctness of the design. It is important that the symbolic simulation may be performed on the same model. Two papers use the technique of checkers to assist in functional verification. One is more practical using checkers selected from the library and an example of a dual-CPU PCI bridge. In another a method for reducing the state space by transforming design to synchronous form is presented. In another paper a random simulation guided by genetic algorithms is used for supporting design verification.
Synthesis (3 papers). The following synthesis issues have been considered: flip-flop inference problem coping with complex clocked statements, object integration into VHDL addressed especially to communication modeling and synthesis, transformation of VHDL models (although interesting from the theoretical point of view it is not clear what is the goal of this transformations).
Specification formalisms (7 papers). The main issues in the approach to specification are the following: 1) Heterogeneity in design process causing the necessity of multiple perspectives and multiple modeling paradigms. As a remedy the Rosetta language is devised. Rosetta addresses a need for a language in which designers can specify the requirements and constraints on diverse (electronic, mechanical, optical, etc.) systems.
2) Methodology for transformation of system level description into behavior and structure illustrated by ATM (Asynchronous Transfer Mode) switch.
3) Asynchronous process and their models. To this theme belongs the specific problem of 4-phase hand-shaking asynchronous controller specification and its idle-phase optimization.
4) Reactive (opposed to interactive) systems, for which a behavioral specification model based on formal entities called agents has been developed.
5) Java extension making language more useful for the design of reactive and embedded systems.
Tool performance (4 papers). The first paper presents experience and economical analysis of test generation for testing adherence of HDL tools like compilers to vendor-neutral VHDL or Verilog specifications. Next papers present: methodology for embedded software power estimation, synthetic data on performance trade-offs for emulation, hardware acceleration and simulation, a framework for reusable run-time scripting in Tcl.
Systems-On-Chip (SOC) design and reuse (5 papers). In this section more general papers influenced by design trends are included. Object-orientation is the aim of the first paper in which it is used for specification and design of embedded real-time systems. Next paper presents experience in developing and applying function-architecture co-design methodologies and technology. Function architecture is a system level design methodology in which the function is explicitly mapped to the architecture, during which time all required hardware-software, hardware-hardware, and software-software partitioning is carried out. Further paper describes the roadmap for design automation elaborated by MEDEA (Micro-Electronics Development for European Applications). It is a forecast how design automation of semiconductor manufacture could evolve in Europe, considering shortages in industrial development but also a tremendous reservoir of knowledge. In another paper interface specification framework based on the ideas from the SLIF (System Level Interface Standard) elaborated by VSI Alliance is presented. Last paper presents some remarks on IP (Intellectual Property) reuse in virtual component HW/SW co-design.
This book is recommended to researchers and developers working in the field of automation of hardware design. It provides a broad review of current issues and trends in this field.