Summary: Neural networks (NNs), as processors of time-sequence patterns, have been successfully applied to several speaker-dependent speech recognition systems. This paper develops efficient pipelined neural networks (PNN) architectures, which include both parallel and serial data flow processing stages. Only three types of building units easily matched to the VLSI medium are used in the architecture. Implementing some typical NN models for speech recognition, e.g., time-delay neural networks (TDNN), block-windowed neural network (BWNN) and dynamic programming neural network (DNN), our architecture proposed can greatly reduce the hardware complexity while maintaining a high throughput rate. We analyze the performances of the architecture and illustrate its effectiveness in this paper.