Kindle Notes & Highlights
the true joy in learning Analog design comes from understanding the foundational principles behind how circuits are synthesized, and not merely on how to analyse them.
MOSFETs (or more generally ‘Active’ devices) have a controlling terminal which can alter their I-V characteristics.
In fact, such a circuit is actually the familiar digital inverter attempting to behave like an analog buffer.
small change in the input (stimulus) can potentially shift the operating point of the circuit by a huge amount.
first determine how exactly you want each MOSFET in the circuit to operate, and then connect it up in the manner that makes it behave the way you want it to.
The Holy Grail of Analog design can be summed up as a quest for an elusive component– the Ideal buffer.
Another property of the ideal current source is that it has an infinite output impedance
The equation that determines the drain current Id of the NMOS transistor is:
Note that Id has a dependence on both Vin (which is VGS) as well as Vo (which is VDS
the dependence of Id on Vo suggests that the MOS transistor behaves like a non-ideal current source. Its drain current has a weak dependence on the terminal voltage VDS
While the dependence on VGS (or Vin) is quadratic, the dependence on VDS (or Vo) is linear.
usually Lambda is <<1, making the dependence of Id on VDS weak.
quadratic dependence on VGS
if VDS is high enough, the MOS transistor will be in the Saturation region.
to be noted that the equation we wrote for Id only models its operation in the Saturation region.
the Linear and Deep triode regions, Id has a strong dependence on VDS
while operating in the Saturation region, the MOS transistor has a High sensitivity to VGS (Vin) and a Low sensitivity to VDS
The important thing to keep in mind regarding the PMOS transistor is that the ‘Terminal voltage’ is VSD, the voltage from Source to Drain.
The current flow direction is from Source to Drain.
the NMOS transistor source terminal is connected to GND (the lowest potential), the PMOS transistor source terminal is connected to VDD (the highest potential).
controlling voltage is the difference between the Source and the Gate.
one of the key challenges of Analog design is to get each transistor to operate in its desired operating zone – usually the saturation region.
The method to get all transistors to operate at their desired operating zones is what is called Biasing.
The words “Common source” qualifies the fact that the source terminals are connected to a constant potential (for the NMOS, this potential is ground and for the PMOS it is VDD).
both the input and output are referred to the common terminal which is the source.
“In a relationship, you may not be able to react with the right response every time…”
“… but you always know!”
The PMOS transistor connected in the above manner (with its drain and gate connected) is referred to as a Diode-connected transistor.
A buffer maybe modelled as shown below using a voltage controlled voltage source(.Vin)in
PMOS transistor: VSG = g(Id) where ‘g’ is the inverse function of ‘f’. The function g(Id) is the one shown below (for the PMOS transistor).
current Id forced through it dictates its VSG. Since the source node of the PMOS is driven to VDD, the current is therefore ‘dictating’ the voltage on the Gate node, which is nothing but the output Vo! So the PMOS behaves like a Current-Controlled Voltage Source at Vo!
Whether a transistor in an analog circuit behaves like a current source or a voltage source is determined by whether what is forced is the controlling voltage or the current through it.
When VGS is forced, the transistor behaves like a current source at its Drain. When Id is forced, the transistor behaves like a volta...
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The NMOS transistor that we have stacked on top in this manner is referred to as a gm-load.
2 parameters of interest: gm and gds. These 2 parameters are referred to as small signal parameters since they refer to the response of the MOSFET to a small change applied around the operating point.
if VDS changes by a small amount, the change in current is very small – this is because of the very gentle slope of the Id-VDS curves in the saturation region. This change is depicted by the small-signal parameter called gds. Delta Id = gds* (Delta VDS
So the operating point moves along the same VGS curve.
If VGS changes (VDS remaining constant), then the operating point would ‘jump’ to a VGS curve corresponding to the new VGS. Since Id has a strong dependence on VGS in the saturation region, the change in Id due to a change in VGS would be relatively high. This is depicted by the small-signal parameter called gm. Delta Id = gm* (Delta VGS)
the equation depicts the change in Id if only VGS is changed (with VDS remaining constant). So the operating point jumps vertically.
gm should be much higher than gds. In fact, the ratio of gm/gds is a measure of the inherent ‘gain’ of the transistor.
The exact value of gm/gds depends on the Silicon process and the type of transistor, but for now let us think of a number in the range of 10-20.
a small increase in VGS has to be offset by a large decrease in VDS. gm * (Delta VGS) = -gds * (Delta VDS) This leads us to: Delta VDS = -(gm/gds)*(Delta VGS)
Delta Vout = -gmN/(gdsN+gdsP)
