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Comparison of noise tolerant precharge (NTP) to conventional feedback keepers for dynamic logic

Published: 28 April 2003 Publication History

Abstract

Dynamic logic requires some sort of keeper to prevent the output node from floating and to provide acceptable noise immunity. A number of recent papers have advocated using a very weak complementary pMOS network in place of the conventional feedback keeper; such a technique is called Noise-Tolerant Precharge (NTP). This paper compares the delay and noise margin of NTP with conventional feedback keepers. Although NTP is more robust in that it can recover from a dynamic noise event, it is also 5-50% slower than conventional feedback keepers with the same static noise margin.

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  • (2007)Dynamic gates with hysteresis and configurable noise tolerance2007 IFIP International Conference on Very Large Scale Integration10.1109/VLSISOC.2007.4402495(184-189)Online publication date: Oct-2007

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  1. Comparison of noise tolerant precharge (NTP) to conventional feedback keepers for dynamic logic

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    cover image ACM Conferences
    GLSVLSI '03: Proceedings of the 13th ACM Great Lakes symposium on VLSI
    April 2003
    320 pages
    ISBN:1581136773
    DOI:10.1145/764808
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 28 April 2003

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    Author Tags

    1. dynamic logic
    2. keepers
    3. static noise margin

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    GLSVLSI03: Great Lakes Symposium on VLSI 2003
    April 28 - 29, 2003
    D. C., Washington, USA

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    • (2007)Dynamic gates with hysteresis and configurable noise tolerance2007 IFIP International Conference on Very Large Scale Integration10.1109/VLSISOC.2007.4402495(184-189)Online publication date: Oct-2007

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