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View all- Santhanam KStevens K(2007)Dynamic gates with hysteresis and configurable noise tolerance2007 IFIP International Conference on Very Large Scale Integration10.1109/VLSISOC.2007.4402495(184-189)Online publication date: Oct-2007
Scaling of single-gate MOSFET faces great challenges in the nanometer regime due to the severe short-channel effects that cause an exponential increase in the sub-threshold and gate-oxide leakage currents. Double-gate FinFET technology mitigates these ...
Operating CMOS circuits at subthreshold supply voltages is an attractive solution for substantial energy reduction, at the expense of strong timing performance degradation, for a broad range of battery operated appliances. One of the challenges of this ...
Nanoscale SRAM memory design has become increasingly challenging due to the reducing noise margins and increased sensitivity to threshold voltage variations. These issues oppose our ability to achieve stable bitcells and acceptable performance while ...
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