research-article

Software canaries: software-based path delay fault testing for variation-aware energy-efficient design

Authors:

Rakesh KumarAuthors Info & Claims

ISLPED '14: Proceedings of the 2014 international symposium on Low power electronics and design

Pages 159 - 164

https://doi.org/10.1145/2627369.2627646

Published: 11 August 2014 Publication History

Abstract

Software-based path delay fault testing (SPDFT) has been used to identify faulty chips that cannot meet timing constraints due to gross delay defects. In this paper, we propose using SPDFT for a new purpose -- aggressively selecting the operating point of a variation-affected design. In order to use SPDFT for this purpose, test routines must provide high coverage of potentially-critical paths and must have low dynamic performance overhead. We describe how to apply SPDFT for selecting an energy-efficient operating point for a variation-affected processor and demonstrate that our test routines achieve ample coverage and low overhead.

References

[1]

K. Bowman, J. Tschanz, C. Wilkerson, S. Lu, T. Karnik, V. De, and S. Borkar. Circuit techniques for dynamic variation tolerance. In DAC, pages 4--7, 2009.

Digital Library

[2]

T. Burd, S. Member, T. Pering, A. Stratakos, and R. Brodersen. A dynamic voltage scaled microprocessor system. IEEE Journal of Solid-State Circuits, 11(35):1571--1580, 2000.

[3]

N. Choudhary, S. Wadhavkar, T. Shah, H. Mayukh, J. Gandhi, B. Dwiel, S. Navada, H. Najaf-abadi, and E. Rotenberg. Fabscalar: Composing synthesizable rtl designs of arbitrary cores within a canonical superscalar template. In ISCA, 2011.

Digital Library

[4]

K. Christou, M. K. Michael, P. Bernardi, M. Grosso, E. Sanchez, and M. Sonza Reorda. A novel sbst generation technique for path-delay faults in microprocessors exploiting gate- and rt-level descriptions. In VTS, pages 389--394, 2008.

Digital Library

[5]

S. Das, C. Tokunaga, S. Pant, W. Ma, S. Kalaiselvan, K. Lai, D. Bull, and D. Blaauw. Razor II: In situ error detection and correction for PVT and SER tolerance. Proc. ISSCC, pages 400--622, 2008.

[6]

S. Dhar, D. Maksimovic, and B. Kranzen. Closed-loop adaptive voltage scaling controller for standard-cell ASICs. ISLPED, 2002.

Digital Library

[7]

A. Drake, R. Senger, H. Deogun, G. Carpenter, S. Ghiasi, T. Nguyen, N. James, M. Floyd, and V. Pokala. A distributed critical-path timing monitor for a 65nm high-performance microprocessor. In ISSCC, pages 398--399, 2007.

[8]

D. Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pant, Rajeev Rao, Toan Pham, Conrad Ziesler, David Blaauw, Todd Austin, Krisztian Flautner, and Trevor Mudge. Razor: A low-power pipeline based on circuit-level timing speculation. In MICRO, pages 7--18, 2003.

Digital Library

[9]

M. Fojtik, D. Fick, Y. Kim, N. Pinckney, D. Harris, D. Blaauw, and D. Sylvester. Bubble razor: An architecture-independent approach to timing-error detection and correction. In ISSCC, pages 488--490, 2012.

[10]

M.S. Gupta, K.K. Rangan, M.D. Smith, Gu-Yeon Wei, and D. Brooks. Decor: A delayed commit and rollback mechanism for handling inductive noise in processors. In HPCA, pages 381--392, 2008.

[11]

Sankar Gurumurthy, Ramtilak Vemu, Jacob A. Abraham, and Daniel G. Saab. Automatic generation of instructions to robustly test delay defects in processors. In ETS, pages 173--178, 2007.

Digital Library

[12]

V. Gutnik and A. Chandrakasan. An efficient controller for variable supply-voltage low power processing. IEEE Proc. Symposium on VLSI Circuits, pages 158--159, 1996.

[13]

Greg Hamerly, Erez Perelman, J. Lau, and Brad Calder. Simpoint 3.0: Faster and more flexible program analysis. In JILP, 2005.

[14]

Andrew Kahng, Seokhyeong Kang, Rakesh Kumar, and John Sartori. Designing processors from the ground up to allow voltage/reliability tradeoffs. In IEEE HPCA, pages 119--129, 2010.

[15]

Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, and John Sartori. Recovery-driven design: Exploiting error resilience in design of energy-efficient processors. IEEE Trans. on CAD of Integrated Circuits and Systems, 31(3):404--417, 2012.

Digital Library

[16]

T. Kehl. Hardware self-tuning and circuit performance monitoring. ICCD, pages 188--192, 1993.

[17]

Wonyoung Kim, D.M. Brooks, and Gu-Yeon Wei. A fully-integrated 3-level dc/dc converter for nanosecond-scale dvs with fast shunt regulation. In ISSCC, pages 268--270, 2011.

[18]

Wonyoung Kim, M.S. Gupta, Gu-Yeon Wei, and D. Brooks. System level analysis of fast, per-core dvfs using on-chip switching regulators. In HPCA, pages 123--134, 2008.

[19]

S. Lee, S. Das, T. Pham, T. Austin, D. Blaauw, and T. Mudge. Reducing pipeline energy demands with local dvs and dynamic retiming. In ISLPED, pages 319--324, 2004.

Digital Library

[20]

Charles R. Lefurgy, Alan J. Drake, Michael S. Floyd, Malcolm S. Allen-Ware, Bishop Brock, Jose A. Tierno, and John B. Carter. Active management of timing guardband to save energy in power7. In MICRO, pages 1--11, 2011.

Digital Library

[21]

Edward McCluskey. Built-in self-test techniques. IEEE Des. Test, 2(2):21--28, March 1985.

Digital Library

[22]

M. Najibi, M. Salehi, A. Afzali Kusha, M. Pedram, S. M. Fakhraie, and H. Pedram. Dynamic voltage and frequency management based on variable update intervals for frequency setting. In ICCAD, pages 755--760, 2006.

Digital Library

[23]

Janak Patel. Cmos process variations: A critical operation point hypothesis, 2008.

[24]

M. Psarakis, D. Gizopoulos, E. Sanchez, and M.S. Reorda. Microprocessor software-based self-testing. Design Test of Computers, IEEE, 27(3):4--19, 2010.

Digital Library

[25]

Smitha Shyam, Kypros Constantinides, Sujay Phadke, Valeria Bertacco, and Todd Austin. Ultra low-cost defect protection for microprocessor pipelines. In ASPLOS, pages 73--82, 2006.

Digital Library

[26]

Virendra Singh, Michiko Inoue, Kewal K. Saluja, and Hideo Fujiwara. Instruction-based self-testing of delay faults in pipelined processors. IEEE TVLSI, 14(11):1203--1215, November 2006.

Digital Library

[27]

Sun. Sun OpenSPARC Project, 2010.

[28]

James Tschanz, Keith Bowman, Chris Wilkerson, Shih-Lien Lu, and Tanay Karnik. Resilient circuits: enabling energy-efficient performance and reliability. In ICCAD, pages 71--73, 2009.

Digital Library

[29]

A.K. Uht. Going beyond worst-case specs with teatime. IEEE Micro Top Picks, pages 51--56, 2004.

Digital Library

[30]

Bardia Zandian, Waleed Dweik, Suk Hun Kang, Thomas Punihaole, and Murali Annavaram. Wearmon: Reliability monitoring using adaptive critical path testing. In DSN, pages 151--160, 2010.

Cited By

Maroudas ELalis SBellas NAntonopoulos CPalesi MTumeo AGoumas GAlmudever C(2021)Exploring the potential of context-aware dynamic CPU undervoltingProceedings of the 18th ACM International Conference on Computing Frontiers10.1145/3457388.3458658(73-82)Online publication date: 11-May-2021
https://dl.acm.org/doi/10.1145/3457388.3458658
Goyal HAgrawal V(2019)Technology Characterization Model and Scaling for Energy ManagementVLSI Design and Test10.1007/978-981-32-9767-8_56(679-693)Online publication date: 18-Aug-2019
https://doi.org/10.1007/978-981-32-9767-8_56

Index Terms

Software canaries: software-based path delay fault testing for variation-aware energy-efficient design
1. Hardware

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cover image ACM Conferences

ISLPED '14: Proceedings of the 2014 international symposium on Low power electronics and design

August 2014

398 pages

ISBN:9781450329750

DOI:10.1145/2627369

General Chairs:
Yuan Xie
UCSB, USA
,
Tanay Karnik
Intel, USA
,
Program Chairs:
Muhammad M. Khellah
Intel, USA
,
Renu Mehra
Synopsys, USA

Copyright © 2014 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 11 August 2014

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ISLPED'14

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ISLPED'14: International Symposium on Low Power Electronics and Design

August 11 - 13, 2014

California, La Jolla, USA

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ISLPED '14 Paper Acceptance Rate 63 of 184 submissions, 34%;

Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

Maroudas ELalis SBellas NAntonopoulos CPalesi MTumeo AGoumas GAlmudever C(2021)Exploring the potential of context-aware dynamic CPU undervoltingProceedings of the 18th ACM International Conference on Computing Frontiers10.1145/3457388.3458658(73-82)Online publication date: 11-May-2021
https://dl.acm.org/doi/10.1145/3457388.3458658
Goyal HAgrawal V(2019)Technology Characterization Model and Scaling for Energy ManagementVLSI Design and Test10.1007/978-981-32-9767-8_56(679-693)Online publication date: 18-Aug-2019
https://doi.org/10.1007/978-981-32-9767-8_56

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