Timeline for The strong-ness of x86 store instruction wrt. SC-DRF?
Current License: CC BY-SA 4.0
7 events
| when toggle format | what | by | license | comment | |
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| Dec 7, 2021 at 3:50 | vote | accept | zanmato | ||
| Dec 7, 2021 at 3:50 | comment | added | zanmato | Thank you Peter. Great answer and follow-up, as always! | |
| Dec 7, 2021 at 3:38 | comment | added | Peter Cordes |
@zanmato: Yeah, I don't know why x86 xchg wouldn't right up there with the fence at the top, fully SC. Good point. It's exactly as strong as what most C++ implementations use for atomic_thread_fence(seq_cst), a lock addl $0, (%rsp). (xchg is equivalent to mfence for everything except weakly-ordered movntdqa loads from WC memory on some microarchitectures. But std:atomic leaves it up to the programmer to manually sfence or mfence after using weakly-ordered stores, and many implementations do use a locked op, not mfence, for atomic_thread_fence).
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| Dec 7, 2021 at 3:27 | comment | added | zanmato |
Thanks for the explanation. I think I get the "they are stronger than they need to be" part. My last confusion is that if we were talking about xchg, wouldn't it be on the very top, i.e., fully SC, of the chart?
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| Dec 6, 2021 at 21:33 | history | edited | Peter Cordes | CC BY-SA 4.0 |
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| Dec 6, 2021 at 21:28 | history | edited | Peter Cordes | CC BY-SA 4.0 |
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| Dec 6, 2021 at 21:22 | history | answered | Peter Cordes | CC BY-SA 4.0 |