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Fabrication of quantum processors in advanced 300 mm wafer-scale complementary metal-oxide-semiconductor (CMOS) foundries provides a unique scaling pathway towards commercially viable quantum computing with potentially millions of qubits on a single chip. Here, we show precise qubit operation of a silicon two-qubit device made in a 300 mm semiconductor processing line. The key metrics including single- and two-qubit control fidelities exceed 99% and state preparation and measurement fidelity exceeds 99.9%, as evidenced by gate set tomography (GST). We report coherence and lifetimes up to $T_\mathrm{2}^{\mathrm{*}} = 30.4$ $\mu$s, $T_\mathrm{2}^{\mathrm{Hahn}} = 803$ $\mu$s, and $T_1 = 6.3$ s. Crucially, the dominant operational errors originate from residual nuclear spin carrying isotopes, solvable with further isotopic purification, rather than charge noise arising from the dielectric environment. Our results answer the longstanding question whether the favourable properties including high-fidelity operation and long coherence times can be preserved when transitioning from a tailored academic to an industrial semiconductor fabrication technology.

Superior computational power promised by quantum computers utilises the fundamental quantum mechanical principle of entanglement. However, achieving entanglement and verifying that the generated state does not follow the principle of local causality has proven difficult for spin qubits in gate-defined quantum dots, as it requires simultaneously high concurrence values and readout fidelities to break the classical bound imposed by Bell's inequality. Here we employ heralded initialization and calibration via gate set tomography (GST), to reduce all relevant errors and push the fidelities of the full 2-qubit gate set above 99 %, including state preparation and measurement (SPAM). We demonstrate a 97.17 % Bell state fidelity without correcting for readout errors and violate Bell's inequality with a Bell signal of S = 2.731 close to the theoretical maximum of $2\sqrt{2}$. Our measurements exceed the classical limit even at elevated temperatures of 1.1 K or entanglement lifetimes of 100 $\mu s$.

Quantum processors based on integrated nanoscale silicon spin qubits are a promising platform for highly scalable quantum computation. Current CMOS spin qubit processors consist of dense gate arrays to define the quantum dots, making them susceptible to crosstalk from capacitive coupling between a dot and its neighbouring gates. Small but sizeable spin-orbit interactions can transfer this electrostatic crosstalk to the spin g-factors, creating a dependence of the Larmor frequency on the electric field created by gate electrodes positioned even tens of nanometers apart. By studying the Stark shift from tens of spin qubits measured in nine different CMOS devices, we developed a theoretical frawework that explains how electric fields couple to the spin of the electrons in increasingly complex arrays, including those electric fluctuations that limit qubit dephasing times $T_2^*$. The results will aid in the design of robust strategies to scale CMOS quantum technology.