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Si/SiGe heterostructures are of high interest for high mobility transistor and qubit applications, specifically for operations below 4.2 K. In order to optimize parameters such as charge mobility, built-in strain, electrostatic disorder, charge noise and valley splitting, these heterostructures require Ge concentration profiles close to mono-layer precision. Ohmic contacts to undoped heterostructures are usually facilitated by a global annealing step activating implanted dopants, but compromising the carefully engineered layer stack due to atom diffusion and strain relaxation in the active device region. We demonstrate a local laser-based annealing process for recrystallization of ion-implanted contacts in SiGe, greatly reducing the thermal load on the active device area. To quickly adapt this process to the constantly evolving heterostructures, we deploy a calibration procedure based exclusively on optical inspection at room-temperature. We measure the electron mobility and contact resistance of laser annealed Hall bars at temperatures below 4.2 K and obtain values similar or superior than that of a globally annealed reference samples. This highlights the usefulness of laser-based annealing to take full advantage of high-performance Si/SiGe heterostructures.

Gate-layouts of spin qubit devices are commonly adapted from previous successful devices. As qubit numbers and the device complexity increase, modelling new device layouts and optimizing for yield and performance becomes necessary. Simulation tools from advanced semiconductor industry need to be adapted for smaller structure sizes and electron numbers. Here, we present a general approach for electrostatically modelling new spin qubit device layouts, considering gate voltages, heterostructures, reservoirs and an applied source-drain bias. Exemplified by a specific potential, we study the influence of each parameter. We verify our model by indirectly probing the potential landscape of two design implementations through transport measurements. We use the simulations to identify critical design areas and optimize for robustness with regard to influence and resolution limits of the fabrication process.