Challenges for 3D IC integration: bonding quality and thermal management
P Leduc, F de Crecy, M Fayolle…�- 2007 IEEE�…, 2007 - ieeexplore.ieee.org
In this contribution, two main challenges for wafer-to wafer 3D integration are investigated:
bonding quality (including wafer-to-wafer alignment) and thermal management. The bonding …
bonding quality (including wafer-to-wafer alignment) and thermal management. The bonding …
Fabrication of three-dimensional electrical connections by means of directed actin self-organization
R Galland, P Leduc, C Gu�rin, D Peyrade…�- Nature materials, 2013 - nature.com
A promising approach to improve the performance of microelectronic devices is to build
three-dimensional (3D) chips made of stacked circuits. However, a major hurdle lies in the …
three-dimensional (3D) chips made of stacked circuits. However, a major hurdle lies in the …
Reliability of TSV interconnects: Electromigration, thermal cycling, and impact on above metal level dielectric
T Frank, S Moreau, C Chappaz, P Leduc…�- Microelectronics�…, 2013 - Elsevier
In this paper, reliability of Through Silicon via (TSV) interconnects is analyzed for two
technologies. First part presents an exhaustive analysis of Cu TSV-last approach of 2μm diameter …
technologies. First part presents an exhaustive analysis of Cu TSV-last approach of 2μm diameter …
All-weather vision for automotive safety: which spectral band?
…, O Cassignol, A Nicolas, F Bernardin, P Leduc…�- …�2018: Smart Systems for�…, 2019 - Springer
The AWARE (All Weather All Roads Enhanced vision) French public funded project is aiming
at the development of a low cost sensor fitting to automotive and aviation requirements, …
at the development of a low cost sensor fitting to automotive and aviation requirements, …
Physics of direct bonding: Applications to 3D heterogeneous or monolithic integration
…, H Moriceau, F Grossi, M Rivoire, P Leduc…�- Microelectronic�…, 2010 - Elsevier
Direct wafer bonding and thinning technologies are now extensively used in combination to
produce SOI wafers (silicon-on-insulators) or innovative engineered substrates. Emerging …
produce SOI wafers (silicon-on-insulators) or innovative engineered substrates. Emerging …
Enabling technologies for 3D chip stacking
P Leduc, L Di Cioccio, B Charlet…�- …�Symposium on VLSI�…, 2008 - ieeexplore.ieee.org
This paper presents several key technologies developed for high density 3D integration by
circuit stacking, ie with an inter-strata connection pitch lower than 10μm. Direct bonding …
circuit stacking, ie with an inter-strata connection pitch lower than 10μm. Direct bonding …
Electromigration behavior of 3D-IC TSV interconnects
…, C Chappaz, L Arnaud, P Leduc…�- 2012 IEEE 62nd�…, 2012 - ieeexplore.ieee.org
The electromigration (EM) behavior of Through Silicon Via (TSV) interconnects used for 3D
integration is studied. Impact of the TSV section size on EM lifetime and consideration of …
integration is studied. Impact of the TSV section size on EM lifetime and consideration of …
Modelling of through silicon via RF performance and impact on signal transmission in 3D integrated circuits
…, A Farcy, C Bermond, C Fuchs, P Leduc…�- …�Conference on 3D�…, 2009 - ieeexplore.ieee.org
Through silicon via (TSV) is considered today as the third dimension interconnect opening
new perspectives in term of 3D integration. Design, material and process recommendations …
new perspectives in term of 3D integration. Design, material and process recommendations …
System on wafer: a new silicon concept in sip
…, L Di Cioccio, B Charlet, P Leduc…�- Proceedings of the�…, 2009 - ieeexplore.ieee.org
System integration is clearly a driving force for innovation in packaging. The need for
miniaturization has led to new architectures that combine disparate technologies and materials. …
miniaturization has led to new architectures that combine disparate technologies and materials. …
Reliability approach of high density through silicon via (TSV)
T Frank, C Chappaz, P Leduc, L Arnaud…�- 2010 12th�…, 2010 - ieeexplore.ieee.org
This paper focuses on the link between initial electrical resistance of Through Silicon Via (TSV),
and possible failure occurring during Thermal Cycling Test (TCT) and electromigration (…
and possible failure occurring during Thermal Cycling Test (TCT) and electromigration (…