In this contribution, two main challenges for wafer-to wafer 3D integration are investigated:
bonding quality (including wafer-to-wafer alignment) and thermal management. The bonding …

A promising approach to improve the performance of microelectronic devices is to build
three-dimensional (3D) chips made of stacked circuits. However, a major hurdle lies in the …

In this paper, reliability of Through Silicon via (TSV) interconnects is analyzed for two
technologies. First part presents an exhaustive analysis of Cu TSV-last approach of 2μm diameter …

The AWARE (All Weather All Roads Enhanced vision) French public funded project is aiming
at the development of a low cost sensor fitting to automotive and aviation requirements, …

Direct wafer bonding and thinning technologies are now extensively used in combination to
produce SOI wafers (silicon-on-insulators) or innovative engineered substrates. Emerging …

This paper presents several key technologies developed for high density 3D integration by
circuit stacking, ie with an inter-strata connection pitch lower than 10μm. Direct bonding …

The electromigration (EM) behavior of Through Silicon Via (TSV) interconnects used for 3D
integration is studied. Impact of the TSV section size on EM lifetime and consideration of …

Through silicon via (TSV) is considered today as the third dimension interconnect opening
new perspectives in term of 3D integration. Design, material and process recommendations …

System integration is clearly a driving force for innovation in packaging. The need for
miniaturization has led to new architectures that combine disparate technologies and materials. …

This paper focuses on the link between initial electrical resistance of Through Silicon Via (TSV),
and possible failure occurring during Thermal Cycling Test (TCT) and electromigration (…