Finding the best compromise in compiling compound loops to Verilog
Y Ben-Asher, N Rotem, E Shochat�- Journal of Systems Architecture, 2010 - Elsevier
In this work we consider a special optimization problem involved with compiling compound
loops (combining nested and consecutive sub-loops) to Verilog. Each sub-loop of the
compound loop may require a different optimized hardware configuration (OHC) for
optimized execution times. For example, one loop requires at least two memory ports and
one multiplier for an optimized execution time, while another loop may require only one
memory port but two multipliers, yet one OHC should be selected for both loops. The goal is�…
loops (combining nested and consecutive sub-loops) to Verilog. Each sub-loop of the
compound loop may require a different optimized hardware configuration (OHC) for
optimized execution times. For example, one loop requires at least two memory ports and
one multiplier for an optimized execution time, while another loop may require only one
memory port but two multipliers, yet one OHC should be selected for both loops. The goal is�…
[BOOK][B] Finding the Best Compromise in Compiling Compound Loops to Verilog
E Shochat - 2007 - search.proquest.com
We consider a special optimization problem involved with compiling compound loops
(combining nested and consecutive sub-loops) with array references to Verilog. Each sub-
loop of the compound loop may require a different optimized hardware configuration (OHC)
for optimized execution times. For example, one loop requires at least two memory ports and
one multiplier for an optimized execution time while another loop may require only one
memory port but two multipliers, yet one OHC should be selected for both loops. The goal is�…
(combining nested and consecutive sub-loops) with array references to Verilog. Each sub-
loop of the compound loop may require a different optimized hardware configuration (OHC)
for optimized execution times. For example, one loop requires at least two memory ports and
one multiplier for an optimized execution time while another loop may require only one
memory port but two multipliers, yet one OHC should be selected for both loops. The goal is�…
Showing the best results for this search. See all results