… network layer and they can be easily invoked from an HLS C library. We show that our primitives
running on FPGA clusters can easily saturate a 100 Gbps network … To evaluate EasyNet, …

… capable of implementing 100 Gbps Ethernet connectivity and … EasyNet [6] is a collective
library running with 100 Gbps … The communication is accomplished by means of custom HLS …

… EasyNet and StRoM. The results show that the developed RDMA stack achieves a throughput
of 100 Gbps … Since we are using Xilinx FPGAs, we take the Xilinx Vivado HLS tool as an …

… SmartNIC models at the full line rate of 100 Gbps Ethernet. Particularly, FpgaNIC-enhanced …
HLS (High Level Synthesis), to make it easier to use for software programmers, where HLS …

… High-level synthesis (HLS) tools like Vitis HLS [15] and Intel HLS [12] … We use Ethernet-based
connections offering 100GBps … Compared with EasyNet [39] which also achieves a similar …

… of 100 Gbps, the Ethernet Roadmap by the Ethernet Alliance … requirements are seeing
demands of 400 Gbps to 1 Tbps [74]… to EasyNet and Limago, as the lack of specificity in HLS …

… network established directly via the QSFP ports of the FPGA boards. These ports allow data
transfer with speeds up to 100 GBit/s while open-source network … used from HLS kernels to …

… In this paper the latest generation of the APEnet Network … EasyNet [6] integrates an open
source 100Gbps TCP/IP stack … in a High Level Synthesis (HLS) library. The INFN APE Lab has a …

… built on top of EasyNet [25], an HLS 100 Gbit/s networking stack … streaming interfaces,
along with HLS data structures, it … by Vitis HLS. To overcome the limitation, we exported the …

… We evaluated ACCL+ on an FPGA cluster with 100 Gb/s networking, comparing its performance
… Unfortunately, existing HLSbased libraries lack networking and collective abstractions. …