Design on ESD protection circuit with very low and constant input capacitance
TY Chen, MD Ker�- Proceedings of the IEEE 2001. 2nd�…, 2001 - ieeexplore.ieee.org
TY Chen, MD Ker
Proceedings of the IEEE 2001. 2nd International Symposium on�…, 2001•ieeexplore.ieee.orgEffective on-chip ESD design to solve the ESD protection challenge on the analog pins for
high-frequency or current-mode applications is studied. The device dimension of ESD clamp
devices in analog ESD protection circuit can be reduced to have a much small input
capacitance for high-frequency applications, but it can still sustain a high HBM and MM ESD
level. To find the optimized device dimensions and layout spacings on ESD clamp devices,
a design model is developed to keep the input capacitance as constant as possible (within�…
high-frequency or current-mode applications is studied. The device dimension of ESD clamp
devices in analog ESD protection circuit can be reduced to have a much small input
capacitance for high-frequency applications, but it can still sustain a high HBM and MM ESD
level. To find the optimized device dimensions and layout spacings on ESD clamp devices,
a design model is developed to keep the input capacitance as constant as possible (within�…
Effective on-chip ESD design to solve the ESD protection challenge on the analog pins for high-frequency or current-mode applications is studied. The device dimension of ESD clamp devices in analog ESD protection circuit can be reduced to have a much small input capacitance for high-frequency applications, but it can still sustain a high HBM and MM ESD level. To find the optimized device dimensions and layout spacings on ESD clamp devices, a design model is developed to keep the input capacitance as constant as possible (within 1% variation).
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