Autonomous microrobots have been utilized in a wide range of applications. Energy-efficient, real-time path planning for navigation is essential. This work presents a path-planning processor for 2-D/3-D autonomous navigation. Energy and latency are minimized through algorithm-architecture optimization. The processor utilizes the rapidly exploring random tree (RRT) algorithm to ensure efficient planning on maps that have higher dimensions and a higher resolution. Dual-tree planning, branch extension, and parallel expansion are adopted in order to reduce both computational complexity and memory requirements. A prune-and-reuse strategy is also adopted so as to quickly respond to dynamic scenarios. An array of processing engines (PEs) is deployed in order to enable parallel expansion. The number of PEs is minimized through latency analysis. Low-complexity implementation for the PE is proposed while maintaining a high performance. Fabricated in a 40-nm CMOS technology, the chip integrates 2M logic gates in an area of 3.65 mm ² . The processor supports path-planning tasks for both 2-D and 3-D maps, with latencies of less than 1 and 10 ms, respectively. For a 2-D map that has 100 � 100 grids, the proposed processor dissipates 1.5 μ/task at a clock frequency of 200 MHz from a 0.9-V supply. Compared with the state-of-the-art designs, the proposed path-planning processor achieves a 1467� shorter processing latency based on an energy dissipation that is 2133� lower, despite the capability for larger maps.