Neuflow: A runtime reconfigurable dataflow processor for vision
In this paper we present a scalable dataflow hardware architecture optimized for the computation
of general-purpose vision algorithms - neuFlow - and a dataflow compiler - luaFlow - …
of general-purpose vision algorithms - neuFlow - and a dataflow compiler - luaFlow - …
A 240 g-ops/s mobile coprocessor for deep neural networks
Deep networks are state-of-the-art models used for understanding the content of images,
videos, audio and raw input data. Current computing systems are not able to run deep network …
videos, audio and raw input data. Current computing systems are not able to run deep network …
Hardware accelerated convolutional neural networks for synthetic vision systems
In this paper we present a scalable hardware architecture to implement large-scale convolutional
neural networks and state-of-the-art multi-layered artificial vision systems. This system …
neural networks and state-of-the-art multi-layered artificial vision systems. This system …
Recurrent neural networks hardware implementation on FPGA
AXM Chang, B Martini, E Culurciello�- arXiv preprint arXiv:1511.05552, 2015 - arxiv.org
Recurrent Neural Networks (RNNs) have the ability to retain memory and learn data
sequences. Due to the recurrent nature of RNNs, it is sometimes hard to parallelize all its …
sequences. Due to the recurrent nature of RNNs, it is sometimes hard to parallelize all its …
Embedded streaming deep neural networks accelerator with applications
Deep convolutional neural networks (DCNNs) have become a very powerful tool in visual
perception. DCNNs have applications in autonomous robots, security systems, mobile phones, …
perception. DCNNs have applications in autonomous robots, security systems, mobile phones, …
Large-scale FPGA-based convolutional networks
…, K Kavukcuoglu, E Culurciello, B Martini…�- Scaling up machine�…, 2011 - books.google.com
Many successful object recognition systems use dense features extracted on regularly
spaced patches over the input image. The majority of the feature extraction systems have a …
spaced patches over the input image. The majority of the feature extraction systems have a …
NeuFlow: Dataflow vision processing system-on-a-chip
This paper presents a bio-inspired vision system-on-a-chip - neuFlow SoC implemented in
the IBM 45 nm SOI process. The neuFlow SoC was designed to accelerate neural networks …
the IBM 45 nm SOI process. The neuFlow SoC was designed to accelerate neural networks …
Continuous time level crossing sampling ADC for bio-potential recording systems
…, D Kim, B Goldstein, C Huang, B Martini…�- …�on Circuits and�…, 2013 - ieeexplore.ieee.org
In this paper we present a fixed window level crossing sampling analog to digital convertor
for bio-potential recording sensors. This is the first proposed and fully implemented fixed …
for bio-potential recording sensors. This is the first proposed and fully implemented fixed …
An efficient implementation of deep convolutional neural networks on a mobile coprocessor
…, A Dundar, B Krishnamurthy, B Martini…�- 2014 IEEE 57th�…, 2014 - ieeexplore.ieee.org
In this paper we present a hardware accelerated real-time implementation of deep convolutional
neural networks (DCNNs). DCNNs are becoming popular because of advances in the …
neural networks (DCNNs). DCNNs are becoming popular because of advances in the …
Memory access optimized routing scheme for deep networks on a mobile coprocessor
In this paper, we present a memory access optimized routing scheme for a hardware accelerated
real-time implementation of deep convolutional neural networks (DCNNs) on a mobile …
real-time implementation of deep convolutional neural networks (DCNNs) on a mobile …