An ultra-low-cost ESD-protected 0.65 dB NF+ 10dBm OP1dB GNSS LNA in 0.18-μm SOI CMOS
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2014•ieeexplore.ieee.org
An ESD-protected GNSS LNA, implemented in 0.18 μm SOI CMOS process, uses only one
external series inductor as input matching. The input common-source transistor is biased in
weak inversion region and operates at Class-AB mode, which greatly improves linearity and
saves quiescent current. A bond wire to ground is adopted as source-degeneration and to
realize input matching. Design trade-offs among NF, stability and ESD protection are
analyzed. The LNA achieves an ultra-low NF of 0.65 dB, a power gain of 19.2 dB, an output�…
external series inductor as input matching. The input common-source transistor is biased in
weak inversion region and operates at Class-AB mode, which greatly improves linearity and
saves quiescent current. A bond wire to ground is adopted as source-degeneration and to
realize input matching. Design trade-offs among NF, stability and ESD protection are
analyzed. The LNA achieves an ultra-low NF of 0.65 dB, a power gain of 19.2 dB, an output�…
An ESD-protected GNSS LNA, implemented in 0.18μm SOI CMOS process, uses only one external series inductor as input matching. The input common-source transistor is biased in weak inversion region and operates at Class-AB mode, which greatly improves linearity and saves quiescent current. A bond wire to ground is adopted as source-degeneration and to realize input matching. Design trade-offs among NF, stability and ESD protection are analyzed. The LNA achieves an ultra-low NF of 0.65dB, a power gain of 19.2dB, an output P1dB of +10dBm, while consuming 5.9mA from 2.8V supply. The LNA is housed in a 6-pin LGA package with a die area (including pads) of 0.28mm 2 . It passes 2.5KV HBM, 200V MM and 250V CDM ESD tests.
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