Floorplanning of modules has been a significant role in VLSI design automation and it can be formulated as the "Rectangle Packing Problem." Ising model-based computers (or annealing machines) are the type of a non-von Neumann computer and recently expected to solve combinatorial optimization problems efficiently. In this paper, we propose a mapping of "Rectangle Packing Problem" for solving it by the annealing machines. In our proposed mapping, a sequence-pair is represented on an Ising model. Our proposed approach maps a "Rectangle Packing Problem" with N rectangles onto a 3N ³ -spin logical Ising model. Experimental results demonstrate that through the proposed approach we can solve the problem with 18 rectangles at the maximum on a fully-connected annealing machine and the problem with three rectangles at the maximum on 20k-spin CMOS annealing machine.