A 10Gb/s 10mW 2-tap reconfigurable pre-emphasis transmitter in 65nm LP CMOS
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012•ieeexplore.ieee.org
A low-power pre-emphasis voltage mode transmitter architecture with output swing control,
pre-emphasis coefficient control, and online impedance calibration is proposed and
demonstrated. A 65nm LP CMOS implementation of this architecture dissipates only~ 10mW
from a 1.2 V supply when transmitting 10Gb/s 400mV differential peak-to-peak data with 2-
tap pre-emphasis, achieving 1pJ/bit energy efficiency.
pre-emphasis coefficient control, and online impedance calibration is proposed and
demonstrated. A 65nm LP CMOS implementation of this architecture dissipates only~ 10mW
from a 1.2 V supply when transmitting 10Gb/s 400mV differential peak-to-peak data with 2-
tap pre-emphasis, achieving 1pJ/bit energy efficiency.
A low-power pre-emphasis voltage mode transmitter architecture with output swing control, pre-emphasis coefficient control, and online impedance calibration is proposed and demonstrated. A 65nm LP CMOS implementation of this architecture dissipates only ~10mW from a 1.2V supply when transmitting 10Gb/s 400mV differential peak-to-peak data with 2-tap pre-emphasis, achieving 1pJ/bit energy efficiency.
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