In this paper, we characterize the behavior of TS-based designs in the face of voltage overscaling (or undervolting). We show that the power benefits of TS due�...

ABSTRACT. Processors have traditionally been designed for the worst-case, re- sulting in designs that have high yields, but are expensive in terms.

In this paper, we characterize the behavior of TS-based designs in the face of voltage overscaling (or undervolting). We show that the power benefits of TS due�...

In this paper, we characterize the behavior of TS-based designs in the face of voltage overscaling (or undervolting). We show that the power benefits of TS due�...

Processors have traditionally been designed for the worst-case, resulting in designs that have high yields, but are expensive in terms of area and power.

John Sartori, Rakesh Kumar: Overscaling-friendly timing speculation architectures. ACM Great Lakes Symposium on VLSI 2010: 209-214.

Overscaling-friendly timing speculation architectures. In GLSVLSI, 2010. [23] Sun. Sun OpenSPARC Project. [24] Synopsys. Synopsys Design Compiler User's Manual.

Using timing speculation-aware architectural optimizations, we demonstrate enhanced overscaling and up to 29% additional energy savings for processors that�...

Overscaling-friendly timing speculation architectures. May 2010. John Sartori ... overscaling are greatly determined by the design of the circuit architecture.

Sartori, John, and Rakesh Kumar. "Overscaling-friendly timing speculation architectures." In the 20th symposium. New York, New York, USA: ACM Press, 2010. http�...