This paper presents a novel hierarchical simulation method for analyzing the power network reliability. Instead of performing full-chip simulation at the�...

This paper presents a novel hierarchical simulation method for analyzing the power network reliability. Instead of performing full-chip simulation at the�...

This paper presents a novel hierarchical simulation method for analyzing the power network reliability. Instead of performing full-chip simulation at the�...

This paper presents a novel hierarchical simulation method for analyzing the power network reliability. Instead of performing full-chip simulation at the�...

The results indicate that the proposed method significantly reduces the CPU runtime and memory requirement for power network simulation, maintaining small�...

This paper presents a novel hierarchical simulation method for analyzing the power network reliability. Instead of performing full-chip simulation at the�...

Yi-Min Jiang, Han Young Koh, Kwang-Ting Cheng : HRM - A Hierarchical Simulator for Full-Chip Power Network Reliability Analysis. ISQED 2001: 307-312.

HRM - A Hierarchical Simulator for Full-Chip Power Network Reliability Analysis. 2001, 1043397. Click here to go back to the BANKS homepage. About BANKS�...

DAC, page 760-765. ACM Press, (1999 )HRM - A Hierarchical Simulator for Full-Chip Power Network Reliability Analysis.Y. Jiang, H. Koh, and K. Cheng. ISQED�...

... Test Symposium, 2001, article number 923466, p. 380-385. Conference paper, 2001. HRM - A hierarchical simulator for full-chip power network reliability analysis.