Abstract: A new approach to handle the inductance effect on multiple signal lines is presented. The worst case switching pattern is first identified.
We apply these models to repeater insertion in critical paths and find that, for a single line, the RLC model minimizes delay with fewer number of repeaters�...
Applications to repeater insertion in the critical path chains are demonstrated. For a single line, the RLC model minimizes delay with fewer number of repeaters�...
... They showed that on-chip inductance can decrease the delay, area, and power of the repeater insertion process as compared to an RC line model [35]. Banerjee�...
Effective on-chip inductance modeling for multiple signal lines and application to repeater insertion. by weize xie. 2002, IEEE Transactions on Very Large�...
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Assume that all wires are of the same height h, the width and length of each signal wire are ws and lw respectively, and the overlapping length of two signal.
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(2002), Effective onchip inductance modeling for multiple signal lines and application to repeater Insertion, IEEE Transactions on Very Large Scale�...
Inserting repeaters based on an RC model and neglecting inductance results in a larger repeater area than necessary to achieve a minimum delay.
Introduction. On-chip interconnects are now the primary bottleneck in the flow of signals through high complexity, high speed integrated circuits (ICs).