This work focuses on the interconnect infrastructure, functionality, and capability of a heterogeneous reconfigurable SoC.

This work states that wordor subword-oriented runtime reconfigurable architectures offer highly parallel, scalable solutions combining hardware performance�...

In this paper, we propose a scalable distributed memory system with a low-cost hardware message-passing interface. The proposed interface improves the�...

This article presents a design case study on the interconnect for such a programmable platform, as part of the Morpheus project.

Abstract: Editor's note:The diversification of the SoC market has increased the need for domain-specific programmable platforms that can be tailored to�...

This work focuses on the interconnect infrastructure, functionality and capability of a heterogeneous reconfigurable SoC. The SoC integrates reconfigurable�...

An Interconnect Strategy for a Heterogeneous, Reconfigurable SoC. M. K�hnle, M. H�bner, J. Becker, A. Deledda, C. Mucci, F. Ries, M. Coppola, L. Pieralisi,�...

Abstract—In this paper, we present an overview of interconnect solutions for hardware accelerator systems. A number of solu- tions are presented: bus-based,�...

Characterization of Equalized and Repeated Interconnects for NoC Applications pp. 430-439. An Interconnect Strategy for a Heterogeneous, Reconfigurable SoC pp.

In this paper, we present a novel high-performance re-configurable NoC architecture that can improve the performance along with similar or improved power�...