Abstract
This paper presents methods for efficient optimization of ASIC implementation for H.264/AVC video decoding. A systematic approach in optimization is presented in a top-down flow. Tradeoffs among Power, Throughput, and Area (PTA) at both system level and block level are studied and balanced. The system architecture is first evaluated. We then focus on the pipeline organization, parallelism, and memory architecture optimization. Different pipeline granularities are compared and their pros-and-cons are evaluated. Various parallel scenarios, especially 1 × 4-column and 4 × 1-row, are analyzed and compared. Then the detailed designs of various building blocks, such as inverse transform, inter prediction, and deblocking filter, are evaluated and their intrinsic characteristics are exploited to facilitate PTA optimization. Finally, we provide the design guidelines for ASIC implementation based on the analysis and our design experiences of five dedicated decoder chips.
Similar content being viewed by others
References
Team, J. V. (2003). Advanced video coding for generic audiovisual services. ITU-T Recommendation H.264 and ISO/IEC 14496-10 AVC, May 2003.
Wiegand, T., Sullivan, G. J., Bjontegaard, G., & Luthra, A. (2003). Overview of the H.264/AVC video coding standard. IEEE Transactions on Circuits and Systems for Video Technology, 13(7), 560–576.
Iverson, V., McVeigh, J., & Reese, B. (2004). Real-time H.264/AVC codec on Intel architectures. IEEE International Conference on Image Processing, 2, 757–760.
Moshe, Y., Peleg, N. (2005). Implementation of H.264/AVC baseline decoder on different digital signal processors. 47the International Symposium on ELMAR, pp 37–40, June 2005.
Xu, K., Choy, C. S. (2007). Low-power H.264/AVC baseline decoder for portable applications. International Symposium on Low Power Electronics and Design 256–261.
Liu, T. M., et al. (2007). A 125 µW, fully scalable MPEG-2 and H.264/AVC video decoder for mobile applications. IEEE Journal of Solid-State Circuits, 42(1), 161–169.
Lin, C. C., et al. (2007). A 160 K gates/4.5 KB SRAM H.264 video decoder for HDTV applications. IEEE Journal of Solid-State Circuits, 42(1), 170–182.
Chien, C. D. et al. (2007). A 252kgate/71 mW multi-standard multi-channel video decoder for high definition video applications. IEEE ISSCC Dig. Tech. Papers, 282–283.
Liu, T. M et al. (2005). An 865-µW H.264/AVC video decoder for mobile applications. in Proc. IEEE Asia Solid-State Circuits Conference, 301–304.
Park, S., Cho, H. J., Jung, H., Lee, D. D. (2005). An implemented of H.264 video decoder using hardware and software. IEEE Custom Integrated Circuits Conference, 271–275.
Kang, H. Y., Jeong, K. A., Bae, J. Y., Lee, Y. S., Lee, S. H. (2004). MPEG4 AVC/H.264 decoder with scalable bus architecture and dual memory controller. IEEE International Symposium on Circuits and Systems, 145–148.
Hu, Y., Simpson, A., McAdoo, K., Cush, J (2004). A high definition H.264/AVC hardware video decoder core for multimedia SoC’s. IEEE International Symposium on Consumer Electronics, 385–389.
Chen, T. C., Lian, C. J., Chen, L.G. (2006). Hardware architecture design of an H.264/AVC video codec. Asia and South Pacific Conference on Design Automation, 750–757.
Fujiyoshi, T., et al. (2006). A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic voltage/frequency scaling. IEEE Journal of Solid-State Circuits, 41(1), 54–62.
Lian, C. J., Tseng, P. C., Chen, L. G. (2006). Low-power and power-aware video codec design: an overview. China Communications, 45–51.
Lie, W. N., Yeh, H. C., Lin, T. C. I., & Chen, C. F. (2005). Hardware-efficient computing architecture for motion compensation interpolation in H.264 video decoding. IEEE International Symposium on Circuits and Systems, 3, 2136–2139.
Xu, K. (2007). Power-efficient design methodology for video decoding. PhD Dissertation, The Chinese University of Hong Kong, Aug. 2007.
Liu, T. M. (2007). Study of MPEG-2 and H.264 video decoders for mobile applications. PhD Dissertation, National Chiao Tung University, May 2007.
Chen, T. W., et al. (2005). Architecture design of H.264/AVC decoder with hybrid task pipelining for high definition videos. IEEE International Symposium on Circuits and Systems, 3, 2931–2934.
Huang, Y. W., Chen, T. W., Hsieh, B. Y., Wang, T. C., Chang, T. H., & Chen, L. G. (2003). Architecture design for deblocking filter in H.264/JVT/AVC. International Conference on Multimedia and Expo (ICME’03), 1, 693–696.
Sima, M., Zhou, Y. H., & Zhang, W. (2004). An efficient architecture for adaptive deblocking filter of H.264/AVC video coding. IEEE Transactions on Consumer Electronics, 50(1), 292–296.
Chang, S. C., Peng, W. H., Wang, S. H., & Chiang, T. H. (2005). A platform based bus-interleaved architecture for de-blocking filter in H.264/MPEG-4 AVC. IEEE Transaction on Consumer Electronics, 51(1), 249–255.
Sheng, B., Gao, W., & Wu, D. (2004). An implemented architecture of deblocking filter for H.264/AVC. IEEE International Conference on Image Processing (ICIP’04), 1, 665–668.
Liu, T. M., Lee, W. P., Lin, T. A., Lee, C. Y. (2005). A memory-efficient deblocking filter for H.264/AVC video coding. IEEE International Symposium on Circuits and Systems, 2140–2143.
Liu, T. M., Lee, C. Y. (2007). Design of an H.264/AVC decoder with memory hierarchy and line-pixel-lookahead, Journal of VLSI Signal Processing.
Lou, J., Jagmohan, A., He, D., Lu, L. G., Sun, M. T. (2007). Statistical analysis based H.264 high profile deblocking speedup. IEEE International Symposium on Circuits and Systems, 3143–3146.
Katevenis, M. “On-chip SRAM and power consumption”, lecture notes, Department of Computer Science, Unversity of Crete, Greece, http://archvlsi.ics.forth.gr/~kateveni/534/05a/s21_chip.html
Malvar, H. S., Hallapuro, A., Karczwicz, M., & Kerofsky, L. (July 2003). Low-complexity transform and quantization in H.264/AVC. IEEE Transactions of Circuits and Systems on Video Technology, 13, 598–603.
Gordon, B. M. (1996). Low power video compression for protable applications using subband coding. Ph.D. dissertation, Stanford University, 1996.
Xu, K., Choy, C. S. A power-efficient and self-adaptive prediction engine for H.264/AVC decoding. IEEE Transactions on VLSI Systems, accepted for publication.
Joint Video Team (JVT) reference software JM, available: http://iphome.hhi.de/suehring/tml/download/.
Xu, K., Choy, C. S. A 5-stage Pipeline, 204 Cycles/MB, Single-port SRAM Based Deblocking Filter for H.264/AVC. IEEE Transactions on Circuits and Systems for Video Technology, accepted for publication.
Lappalainen, V., Hallapuro, A., & Hamalainen, T. D. (2003). Complexity of optimized H.26 L video decoder implementation. IEEE Transactions of Circuits and Systems on Video Technology, 13, 717–725.
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Xu, K., Liu, TM., Guo, JI. et al. Methods for Power/Throughput/Area Optimization of H.264/AVC Decoding. J Sign Process Syst Sign Image Video Technol 60, 131–145 (2010). https://doi.org/10.1007/s11265-009-0408-6
Received:
Revised:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s11265-009-0408-6