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Still Image Processing on Coarse-Grained Reconfigurable Array Architectures

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Abstract

Due to the increasing demands on efficiency, performance and flexibility reconfigurable computational architectures are very promising candidates in embedded systems design. Recently coarse-grained reconfigurable array architectures (CGRAs), such as the ADRES CGRA and its corresponding DRESC compiler are gaining more popularity due to several technological breakthroughs in this area. We investigate the mapping of two image processing algorithms, Wavelet encoding and decoding, and TIFF compression on this novel type of array architectures in a systematic way. The results of our experiments show that CGRAs based on ADRES and its DRESC compiler technology deliver improved performance levels for these two benchmark applications when compared to results obtained on a state-of-the-art commercial DSP platform, the c64x DSP from Texas Instruments. ADRES/DRESC can beat its performance by at least 50% in cycle count and the power consumption even drops to 10% of the published numbers of the c64x DSP.

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Acknowledgements

The authors would like to thank Bjorn de Sutter and Bingfeng Mei for their input to this paper.

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Authors and Affiliations

  1. IMEC Leuven, Kapeldreef 75, 3001, Leuven, Belgium

    Matthias Hartmann, Vasileios (Vassilis) Pantazis & Tom Vander Aa

  2. Department of Electrical Engineering, University of Technology Braunschweig, Hans-Sommer-Straße 66, 38106, Braunschweig, Germany

    Mladen Berekovic

  3. Department of Computer Science, University of Technology Dresden, Helmholtzstrasse 10, 01062, Dresden, Germany

    Christian Hochberger

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  1. Matthias Hartmann
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  2. Vasileios (Vassilis) Pantazis
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  5. Christian Hochberger
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Correspondence to Matthias Hartmann.

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Hartmann, M., Pantazis, V.(., Vander Aa, T. et al. Still Image Processing on Coarse-Grained Reconfigurable Array Architectures. J Sign Process Syst 60, 225–237 (2010). https://doi.org/10.1007/s11265-008-0309-0

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