Abstract
On line arithmetic is a computation tool able to adapt to the precision expected by the user. Developing a library of on line operators for FPGAs will lead in a near future to the spread of brick-assembled application-dedicated operators. In the implementation of the basic arithmetic operations (addition, multiplication, division and square root), we have met some new problems: our work has involved changes in the VLSI design methodology in order to achieve some effective performances. We shall present the modified on-line algorithms and their adaptation to the cell oriented FPGA architecture. The correct integration of some retiming barriers has proved to be critical as far as speed is concerned.
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References
A. Avizienis, “Signed digit number representation for fast parallel arithmetic”, IRE Transaction on Electronic Computers, Volume EC-10, 1961.
J.C. Bajard, J. Duprat, S. Kla & J.M. Muller, “Some operators for on-line radix 2 computation”, to appear in Journal of Parallel and Distributed Computing, also available from Laboratoire de l'Informatique du Parallélisme RR 92-42, October 1992.
P. Bertin, D. Roncin & J. Vuillemin, “Introduction to programmable active memories,” Systolic Array Processors, Prentice Hall, also available from Paris Research Laboratory, PRL-RR 24, March 1993.
C.Y. Chow & J.E. Robertson, “Logical design of a redundant binary adder”, 4th IEEE Symposium on Computer Arithmetic, October 1978.
M.D. Ercegovac, “On line arithmetic: an overview”, Real Time Signal Processing VII, SPIE, Volume 495.
-, “A general hardware oriented method for evaluation of functions and computations in a digital computer”, IEEE Transactions on Computers, Volume C-26, N. 7, July 1977.
S. Kla Koué, “Calcul parallèle et en ligne des fonctions arithmétiques,” Laboratoire de l'Informatique du Parallélisme, PhD Dissertation 31–93, February 1993.
M.E. Louie & M.D. Ercegovac, “On digit recurrence division implementations for field programmable gate arrays”, 11th IEEE Symposium on Computer Arithmetic, June 1993.
J.M. Muller, “Some characterization of functions computable in on-line arithmetic,” to appear in IEEE Transactions on Computers, also available from Laboratoire de l'Informatique du Parallélisme RR 91-15, 1991.
K.S. Trivedi & M.D. Ercegovac, “On line algorithm for division and multiplication,” IEEE Transactions on Computers, Volume C-26 (7), July 1977.
Xilinx Inc., “The programmable gate array data book,” Product Briefs, Xilinx, 1987.
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© 1994 Springer-Verlag Berlin Heidelberg
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Daumas, M., Muller, JM., Vuillemin, J. (1994). Implementing on line arithmetic on PAM. In: Hartenstein, R.W., Servít, M.Z. (eds) Field-Programmable Logic Architectures, Synthesis and Applications. FPL 1994. Lecture Notes in Computer Science, vol 849. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-58419-6_90
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DOI: https://doi.org/10.1007/3-540-58419-6_90
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